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fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
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fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
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dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
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m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
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正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
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matlab下，用dspbuilder实现dds模块产生正弦波的源码，-Matlab and used to achieve dds dspbuilder produce sine module source code,
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verilog语言例题集锦
包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
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由MATLAB生成的RTDX的源代码，由模型搭建，然后自动生成DSP的源代码-RTDX generated by MATLAB source code, set up by the model, and then automatically generate DSP source code
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数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
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ps2 keyboard verilog source code, to support the ascii code. scan code output, the expansion of key output, press and release the information output
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《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。-" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of
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关于《无线通信FPGA设计》的源代码，有matlab和fpga的实现，非常好，特别是对于做信号处理的。-On " Wireless Communications FPGA design" of the source code, there is matlab and fpga implementation, very good, especially for doing signal processing.
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一种基于verilog的fir滤波源码，并带matlab仿真源程序。-Based on the fir filter verilog source code and source code with matlab simulation.
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matlab源代码很有用那个的软件，配合许多电子软件使用-matlab source code
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使用Matlab和Verilog实现fibonacci序列，包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
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设计一个8位的CPU 有完整的程序包 仿真结果-Modern communication system ( MATLAB ) Edition ( Second Edition ) MATLAB+ source code for all
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《无线通信FPGA设计》书的源代码 ，包括matlab和verilog~-FPGA design of wireless communication book source code, to include matlab and verilog ~~
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快速傅里叶变换（FFT）的verilog源代码以及matlab代码-Fast Fourier Transform (FFT) of the verilog source code and matlab code
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QPSK调制解调，载波同步的matlab源程序，测试通过无bug-QPSK modulation and demodulation, carrier synchronization matlab source code, test bug-
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无线通信模块设计FPGA代码 包括matlab模型文件及verilog源代码-The wireless communication module design including FPGA code matlab verilog model file and source code
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