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mlite.tar
- Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
CPU
- verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
MIPS_CPU
- 一个完整的MIPS CPU的设计，是创新设计项目，内含详细的项目设计报告-A complete MIPS CPU design, innovative design projects, detailed project design report containing
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
mipsCPU
- MIPS CPU tested in Icarus Verilog
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
CU
- mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.
MIPS-CPU
- 完整的32位MIPS处理器工程，拥有整个工程和doc文件说明-Full 32-bit MIPS processor works with the entire project and doc file descr iption
mips
- mips verilog进行编写cpu,其中包括了若干的基本指令(use the verilog language to programme the CPU)
mips-cpu-master
- MIPS Implementation in Verilog. Full source code!
mips-cpu-master
- CPU设计，已通过模拟，有需要的自行下载吧(CPU design has been simulated)