搜索资源列表
MIPS
- 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
CU
- mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
mipsfinal
- 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
instruction_decode_v
- MIPS 5 stage pipeline, this file is for instruction decode. you can use it to place in pipline. this has been used in a study lab.
MIPS32
- MIPS32指令集兼容的CPU模拟器设计 健词：MIPs处理器；模拟器；高速缓存；分支预-of CPU Simulator Compatible with MIPS32 Instruction Set A design scheme of a CPu simulator which is compatjble with MIPS32 instruction set is presented．
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
ALU
- 11条指令MIPS指令系统CPU中的ALU设计-11 instruction in the MIPS instruction ALU design in the system CPU
CPU_design
- 微机原理32位微处理器设计。可以完成基本的MIPS指令。-Microcomputer Principle 32 of the microprocessor design. You can complete the basic MIPS instruction.
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.
single-CPU
- 单时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Single CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
cpu
- 用vhdl实现了具有流水的cpu，实现30条基于mips指令的指令集-Achieved with vhdl cpu with water, to achieve 30 mips instruction based instruction set
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran
MIPS
- 用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies th
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
mipsx2
- 基于FPGA的SOC设计与功能测试，利用mips指令集编写的soc片上系统，以及功能验证- SOC design and FPGA-based functional test, use mips instruction set written soc system on a chip, and functional verification
32-bit-RISC
- 基于MIPS指令集的32位RISC处理器逻辑设计的论文，讲的非常详细适合初学者学习。-32-bit RISC processor logic based on MIPS instruction set design paper, speak very detailed is suitable for beginners to learn.
soc_sram_func
- 利用verilog编写的32位 MIPS指令集CPU，sram接口，已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)