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伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
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伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
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伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
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伪二进制随机码的产生，在fpga上已经验证-Pseudo-random binary code generation
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8位伪随机序列发生器设计，可以进行时序仿真和功能仿真-The design of 8 bits Pseudo-Random Binary Sequence,you can do Timing simulation and function simulation
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基于verilog产生伪随机二进制序列，序列速率为5M(A pseudo-random binary sequence based on verilog.)
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