搜索资源列表
IIS_VHDL
- VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
8051-vhdl-code
- 单片机8051 IP内核的VHDL源码，需要的开发环境QUARTUS II 6.0。
6-portRegisterFile
- 6端口寄存器IP内核VHDL源代码，所需的开发环境是QUARTUS II 6.0。
BIST_Circuits
- BIST 电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
SoC_WishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
core_arm.tar
- ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
keyboardcontroller.tar
- 键盘控制电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
sdram_ctrl.tar
- SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
quartus6.0
- Atlera 公司的开发软件平台quartus 6.0的license
QuartusII
- 介绍Quartus II 6.0使用指南。哈尔滨工程大学信息与通信工程学院
fifo8_8
- 8*8位的fifo数据缓冲器的vhdl源程序。经过quartus ii 6.0 验证成功。
VGAdisplay
- VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208-VHDL entry experiment. 256-color VGA display driver development software Quartus II 6.0 chip EP2c8Q208
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
Cymometer
- Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Altera_Quartus_6.0_crack
- fonctional crack of VHDL describer Quartus 6.0
tutorial
- quartus ii 6.0版本tutorial文件，在不同的版本中会出现不同的说明介绍，包括6.0/ 7.2/ 8.0。-tutorial for quartus ii 6.0 that illustrate a quiker way to get access of basic feature of the design software
DA
- 基于EP1C6Q240的DA转换程序代码，简单易懂，调试通过，基于quartus 6.0-The DA conversion based EP1C6Q240 code, easy to understand, debug through, based on quartus 6.0
clock_for_6.0
- 基于FPGA的电子钟，开发环境是Quartus II 6.0。功能是3个按键分别设置时分秒。通常作为课程设计，供同学参考~-Electronic bell, development environment based on FPGA Quartus II 6.0. The function is the three buttons to set the hour, minute and second. Usually as courses designed for students to ref
VHDL程序
- 利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)