搜索资源列表
round_robin_vhdl
- Round Robin using VHDL
round_three_stage
- 3 stage round arbiter using verilog
round_robin_arbiter
- Round Robin Bus Arbiter for 5-node 8-bit bus
Operating_Systems
- The folder includes various algorithms of Operating Systems such as Bankers algorithm,C-Scan,FIFO,Shortest job first,Round Robin etc. All are implemented in C.
song
- 基于EDA的音乐播放器，可实现几种循环方式-EDA-based music player, enabling several round-robin fashion
Verilog-Round-Robin-Arbiter-Model.tar
- Verilog Round Robin Arbiter Model
3
- Round-robin arbiter的行为。状态机的输入为Reset、CYC0、CYC1和CYC2，输出为GNT0、GNT1和GNT2。任选以下任一方式描述此状态机：-Round-robin arbiter
inputmodule
- synthesis report for round robin
arb
- verilog round robin arbiter
arbiter2
- The logic design of an efficient and fast round robin arbiter in Verilog or any other HDL language relies on the capability to find the next requestor to grant without losing cycles and with minimal logical stages. Using the fastest logic constructs
RR_SCH(Executable)
- FPGA VERILOG调度器一般包括SP、RR、WRR、WFQ等，RR调度指的是轮询调度，此种调度不带权重概念，均匀轮询进行调度。-FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
scalable_arbiter_latest.tar
- a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.
round_robin
- Round Robin priority arbiter
Weighted-Round-Robin-Arbiter-master
- 带权重的优先级轮转算法的verilog实现(Verilog implementation of priority rotation algorithm with weight)