搜索资源列表
primetime
- 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
FPGA_DE2_MUSIC
- 基于FPGA的乐曲硬件演奏模块设计，利用硬件描述语言设计符合技术指标的乐曲硬件发生模块，建立实验模型，通过电路仿真和下载硬件测试，在DE2 EDA实验平台上验证其功能-FPGA-based music performance modular design of hardware, using hardware descr iption language designed to meet specifications of the piece of hardware modules occurs,
verilogFIR
- 本源码为Verilog的FIR数字滤波器 测试后性能很不错的-The source of the FIR digital filter for the Verilog test performance is very good
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
all_packages_20080525.tar
- FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We hav
music
- 乐曲硬件演奏电路设计 由顶层文件和数控分频、乐曲简谱码对应的分频预置数查表电路、8位二进制计数器（ROM的地址发生器）组成。演奏乐曲“梁祝”，乐曲可改。已经过硬件下载测试（使用芯片EP1C6Q240 Cyclone系列）-Music by the top hardware performance circuit design file and the NC frequency, music notation code number corresponding to the preset fr
beep
- 用于蜂鸣器音乐演奏测试程序，可以根据实际需要更改程序！-Music performance test procedures for the buzzer, you can change the program according to actual needs!
fifo
- 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
USB11
- 用NIOS II写的USB 11代码，经板级测试性能良好-With the NIOS II USB 11 code written by the good performance of board-level test
ESS_GZ_V4.6
- 测试工装 电磁环境模拟器测试工装能够产生脉冲宽度、重复频率、输出信号功率可设置的射频脉冲信号及收发组件的各种输出信号，用于模拟器整机和信号采集处理单元的功能和性能测试。-Test fixtures Electromagnetic environment simulator test fixtures can produce pulse width and repeat frequency, the output signal power can be set rf pulse signa
DC-motor-controller-and-its-control
- 基于VHDL语言的直流电机控制器及其控制，本控制系统的总体结构,下位机是整个高频疲劳试验机控制器的核心。用于实现产生控制试验机的控制信号和数据，反馈信号的处理，以及和上位机进行数据通信。其控制功能强弱也直接影响着整个控制器性能的好坏-DC Motor Based on VHDL controller and its control, the overall structure of the control system, the next bit machine is the high-freq
UART_final
- 利用vhdl硬件描述语言，模拟异步通用串行接口UART的通信方式，已在fpga上实际测试，通信性能不错，有一定的参考学习价值！-Using vhdl hardware descr iption language, simulated UART asynchronous serial interface common means of communication, the actual test in fpga, communication performance is good, there i
All-DigitalQPSK-Demodulator
- Altem公司quartus II 8．1开发环境下，完成了中频全数字解调器的FPGA实现，并对数 字下变频、载波同步、位同步等解调器的核心模块设计进行了详细的分析和说明，给出 了实现框图和仿真波形。同时在本设计中应用了Altera公司的NiosII软核处理器技术， 用于载波的大频偏校正和解调器各个部分的监测和控制。最后给出了QPSK中频全数字 解调器关键性能指标的测试方法和测试结果，测试结果表明本设计达到了预期的性能指 标要求。-The Algorithm is con
adder128x
- 128位加法器优化设计：64位加法运算+2-1多路选择器。并在关键路径上添加寄存器，降低延迟。 testbench可以测试优化的效果，在ISE中做过综合，能跑到200+MHz-128-bit adder optimization design: 64-bit adder+ 2-1MUX. In the key path, there are regs to improve the performance and reduce the delay time. you use the tes
CYDOWN
- USB FIFO 测试，为测试USB数据传输的性能-USB FIFO test for the performance of the USB transmit
Bulkloop
- USB FIFO 测试，测试USB的传输性能-USB FIFO test for performance of the USB’s transmission
CIC_bishe
- 测试CIC滤波器的基本性能,并对CIC滤波器做进一步说明！-To test the basic performance of the CIC filter, and the CIC filter to do further!
wei_xulie
- 为序列发生器，数字系统传输性能分析设计，做眼图测试用-Sequence generator, digital transmission performance of system analysis and design, make eye test
hierarchical-code
- Abstract—This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically ad
da900
- FPGA控制DA芯片产生周期信号,用于简单测试芯片性能-DA chip FPGA control signal generation period, for the simple test chip performance