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3下载：
verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
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Viterbi译码的VHDL代码，并且附有详细说明-Viterbi decoding of the VHDL code, and accompanied by a detailed descr iption
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paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the
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verilog code for viterbi encoder and decoder
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This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
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