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sram读模块基于FPGA的实现
- sram读模块基于FPGA的实现 verilog源代码,sram
SRAM.rar
- 瑞芯科技EFX400SL开发板上使用SRAM的工程源码,Rockchip EFX400SL the development of science and technology the use of SRAM on-board source of project
SRAM
- 使用方法： SRAM编程,拷贝到硬盘，用ISE打开工程文件即可-Usage: SRAM programming, copied to the hard drive, open the project file with ISE can
altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
SRAM_Write_read
- SRAM读写的VHDL实验,通过对写入的数据与读出的数据进行比较,判断读写SRAM是否成功-SRAM read and write VHDL experiments on written data and read data to compare, to judge the success of SRAM read and write
EP2C-SOURCE_CODE
- 有關於EP2C的一些程序(EX:I2C,FLASH,IRDA,MUSIC,LED,LIGHT,SRAM,UART,PS2,SPI )-EP2C on some of the procedures (EX: I2C, FLASH, IRDA, MUSIC, LED, LIGHT, SRAM, UART, PS2, SPI)
SRAM_Controller
- SRAM controller用于控制sram -SRAM controller
sram
- 用FPGA 控制sram读写程序的小程序，-fpga control precedure
SRAM_controller
- asynchronus SRAM controller
fpga_sram
- Altera cyclone ep1c6对sram idt71系列的读写时序控制-Altera cyclone ep1c6 of sram idt71 series of read and write timing control
sram
- SRAM implementation source code in VHDL
FGPA-SRAM-Programe
- FPGA编程方法介绍，方便学习VHDL,公供大家参考-fpga programe medoth, study hardware vhdl language
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
sram
- 基于FPGA的SRAM控制程序，里面附加了在线逻辑分析功能的程序，调试时相当的方便-SRAM-based FPGA-control program, which added an online feature of the program logic analysis, debugging very convenient when
IS64LV6416L
- Asynchronous SRAM IS64LV6416L modelsim仿真模型-Asynchronous SRAM IS64LV6416L Verilog model
SRAM
- SRAM源代码，VHDL语言编写，载入可编译，需要的-SRAM source code, VHDL language, incorporated in the compiler, we need to see
sram
- 数据存储和读取电路以一个双端口SRAM为中心，用二进制计数器产生存取地址、以十进制计数器产生欲存储的数据，读出的数据经过LED七段译码，送LED数码管显示-Data storage and reading circuit in a dual-port SRAM as the central access address generated using a binary counter to generate For decimal counter data stored, read out th
SRAM
- 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
SRAM
- 2. FSM is frequently used to design SRAM controller. Given the bubble diagram of a SRAM controller and its state-and-output table as shown below