搜索资源列表
VerilogHDLTestBenchPrimer
- 讲解Verilog 的testbench的书写方法。-on Verilog testbench writing.
WritingTestbenches
- 编写testbench的超好教程,网上这种资料比较少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf
jibengongtestbench
- testbench的基本写法,双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of
TestBench_Primer
- 是学习数字电路设计verilog语言,及Writing testbench的首先好书。-Writing testbench
testbench(vhdl)
- 是学习数字电路设计verilog语言,及Writing testbench的首先好书。-wrting testbench
writing-testbench
- 教你如何写VHDL或VerilogHDL的testbench文件,非常有利于FPGA的波形仿真-Teaches you how to write VHDL or VerilogHDL the testbench file, is very conducive to the waveform simulation of FPGA
Writing-Testbenches-using-System-Verilog
- writing testbench in system verilog
verilog-testbench--technique
- verilog testbench的写法和技巧,适合初学者-Verilog testbench of writing and techniques for beginners
verilog-testbench-preliminary
- 硬件描述语言verilog的testbench的写作方法-the writing method of the testbench of verilog
VHDL-TESTBENCH
- 这是一篇用VHDL编写testbeach测试文件的详细讲解资料,举例讲解详细易懂,很实用-This is a VHDL explain in detail the information writing testbeach test file, for example, to explain in detail to understand, it is practical
testbench_learn
- 自己写的一个移位寄存器的实例,该例子主要用来讲述verilog中的testbench的写作,以及在testbench中怎样使用task,以使仿真更加的高效简洁-Write your own instance of a shift register, which is mainly used to describe examples of verilog testbench writing, as well as how to use the testbench in the task, to m
QAM_verilog
- 基于FPGA的16QAM,用verilog编写,其中DDS为自己编写,含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
verilog add4
- 分两部分,基于verilog的四位和八位加法器设计,用synopsys的VCS仿真工具进行功能仿真,掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)