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8位数字频率计
- 数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
key_scan
- 程序主要是用硬件描述语言(VHDL)实现: 4*4键盘扫描,简洁明了,通俗易懂,比较适合VHDL初学者-procedure was used in hardware descr iption language (VHDL) to achieve : 4 * 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
cpld
- cpld与单片机接口设计,利于电子设计及应用- Interface design between microprocessor and cpld ,suit for IC design and application
cpld_bus
- CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
基于FPGA的李沙育图形发生器
- 这是一个用MAX+PLUSII开发FPGA(1K30器件)开发的李沙育图形发生器(硬件描述语言部分)。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware descr iption language).
一个8位CISC结构的精简CPU
- 一个8位CISC结构的精简CPU,2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
filter 代码
- 用verilog实现滤波器的功能,通过软件综合仿真,在利用FPGA实现-using Verilog filter function to achieve through integrated simulation software, the use of FPGA
发布15个Altera的IP的源码
- ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
alu_vlog
- 学习使用HDL Bencher生成测试积累,并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
Digital_030423
- 服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).-server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD).
Giga8b10b v10
- 可编程器件厂商Altera出品的8b10b编码器,用在现在通用的PCI-Express接口中,包含完全解密的源程序。-Altera programmable device manufacturers buy 8b10b encoder, now with the generic PCI-Express interface, including full decryption of the source.
mi2c
- altera i2c host/device-ALTERA i2c host / device
脉冲记时CPLD
- 工作原理: 脉冲输入,记录30个脉冲的间隔时间(总时间),LED显示出来,牵涉到数码管的轮流点亮,以及LED的码。输入端口一定要用个 74LS14整一下,图上没有。数码管使用共阴数码管。MAXPLUS编译。 测试时将光电门的信号端一块连接到J2口的第三管脚,同时第一管脚为地,应该与光电门的地连接(共地)。 开始测试: 按下按键,应该可以见到LED被点亮,指示可以开始转动转动惯量盘,等遮光片遮挡30次光电门后, LED熄灭,数码管有数字显示,此为时间值,单位为秒,与智
std_cf_2c35
- 这个是基于NIOS II的FPGA平台的一个CF卡的接口模块,是在Quartus II下的完整工程包-NIOS II FPGA platform a CF card interface module, Quartus II is the complete package works
Example-2-5
- 这些是verilog编程实例5,仅供参考-These are examples of Verilog Programming 5 for reference
crc_16
- 循环冗余校验,crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
booth_mul
- 一种可以完成16位有符号/无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法,简化了部分积的符号扩展,采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元,整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to impr
pcm_verilog
- 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
freecore
- 一些vhdl源代码 一些vhdl代码-some VHDL source code for some VHDL source code some VHDL code