搜索资源列表
rtl
- 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
结合XILINXCPLD RS232通信(verilog)
- 结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
8位数字频率计
- 数字频率计~ VHDL 实现 可以实现频率的测量和现实的功能 8位-digtal frequency tester (use vhdl) can be used to test frequency (8bit)
xsoc-beta-093
- This free cpu-ip! use verilog
usbsample
- 基于fpga和xinlinx ise的usb端口vhdl程序，希望对你有所帮助！-VHDL program for USB port based fpga and xinlinx ise, wish help for you!
自定义逻辑PWM的例子
- 是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.
8051verilog源码
- 8051的Verilog-Verilog OF 8051
key_scan
- 程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware descr iption language (VHDL) to achieve : 4 * 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
pinglvhecheng
- 程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
cpld
- cpld与单片机接口设计,利于电子设计及应用- Interface design between microprocessor and cpld ,suit for IC design and application
CORDIC
- 用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.
and_or
- veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
arbit
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
backward
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
bidir
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
bin2gry
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.