H.264解码器，用verilog写成，可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding

H.264解码的源代码，详细介绍各个模块的功能和组成部分。-H.264 decoder source code, and details the function of each module and part.

采用硬件电路的方式实现H.264视频编码标准，包括帧内/帧间预测，熵编码，变换量化等算法-It is achieved using hardware circuitry H.264 video coding standard, including intra/inter prediction, the entropy coding, the quantized transform algorithms