搜索资源列表
fpga-jpeg
- JPEG硬件解码器设计 verilog实现-JPEG hardware decoder design verilog implementation
aes_fifo_interface
- aes to fsl with xilinx fpga
MPEG2_MAC_Verilog_FPGA
- MPEG2+MAC Verilog代码+文档(FPGA实现)-MPEG2+MAC Verilog code the+ document (FPGA implementation)
215057696ofdm_program
- 802.11同步算法的matlab仿真与FPGA实现,非常适合工程应用-802.11 synchronization algorithm matlab simulation and FPGA implementation, very suitable for engineering applications
system_generator
- 其中详细的介绍了matlab中的simulink仿真时ise联合仿真时所用到的system generator的用法,对做fpga很有帮助哦-Described in detail the usage of the system generator used in the joint simulation in matlab simulink simulation ise to do fpga helpful.
09_uart2
- PC机上开串口调试助手,发送一个字符到开发板(中间通过串口线相连) FPGA收到字符后,回发给PC机上,在串口助手上显示 -On the PC, open the serial port on a PC debugging assistant to send a character to the development board (in the middle connected by serial cable) FPGA received character back to the s
12_lcd12864
- 本实验是用LCD12864显示英文 显示 Our FPGA EDA NIOS II SOPC FPGA-This experiment is with LCD12864 show displayed in English Our FPGA EDA NIOS II SOPC FPGA
jpeg_vhdl
- vhdl实现静态图像压缩JPEG的主要程序。基于FPGA芯片。-VHDL fpga
huffman(z)
- HUFFMAN编码,压缩,解压缩,FPGA课设用的-huffman code and encode
frequency-counter
- 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包,解压后可直接下载到DE2板上,其中频率输入端是系统自带27M时钟D13用于测试,如果想要应用于别的开发板,可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompressi
DDS
- VHDL DDS 采用FPGA实现1hz到100khz可调的dds程序,频率调节步长是变化的。-Using FPGA 1hz to 100khz adjustable, dds program, the frequency adjustment step change.
robot_7_31
- 使用Verilog HDL来控制机器人,六个高精密舵机,舵机运动非常流畅,舵机不抖动-FPGA to control the robot servo, six servos
SPIHT-Image-Compression-on-FPGAs
- SPIHT image compression on FPGA
Cholesky
- 7阵元Cholesky分解实现代码,FPGA编程的Matlab对应程序,这是一个子函数,使用时对输入矩阵稍加修改即可-7 elements Cholesky decomposition Matlab corresponding program code, FPGA programming, which is a sub-function, use the input matrix can be slightly modified
mycoe
- 线性调频信号脉冲压缩 用matlab生成coe文件以导入xilinx fpga -Chirp signal pulse compression using matlab generated COE file to import xilinx fpga
sine
- 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能,且数据ROM 在高速条件下,占用最少的逻辑资源,设计流程最便捷,波形数据获最方便。下图是此信号发生器结构图,顶层文件SINGT.VHD 在FPGA 中实现,包含2 个部分:ROM 的地址信号发生器,由5 位计数器担任,和正弦数据ROM,拒此,ROM由LPM_ROM模块构成能达到最优设计,LPM_ROM底层是FPGA中的EAB或ESB等。
PWM-LAB-1
- PWM design using fpga
LMS--FPGA
- The simulink model of Back propagation Algorithm using an Adaptative Filter.
ModelSim_
- FPGA编写环境,具有仿真容易,软件内存小的特点-FPGA authoring environment, with easy simulation software features small memory
cos_value
- 用于生成FPGA中RAM所需要的初始化文件dds.mif,此文件生成的是余弦波形。-This document of .m can generate document of .mif to provide data for RAM of FPGA.