搜索资源列表
fpga-jpeg-Verilog
- jpeg ip核解码器，可以用来解码jpeg，verilog源代码-jpeg ip core for verilog HDL
fft_ly
- 采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of
caculate_variance
- Verilog语言求解均方根的近似方法，用MATLAB仿真实现，思想可移植到FPGA中-Verilog language rms approximate solving method, using MATLAB simulation, ideas can be transplanted into the FPGA
fsk
- 基于fpga的DDS实现,可以实现1hz-40Mhz的正弦信号，方波信号，锯齿波信号，三角波信号等的输出-DDS fpga-based implementation can be achieved 1hz-40Mhz sine signal, square wave signal, sawtooth signal, the output of the triangular wave signal, etc.
generate-mif-file
- 如何生成mif文件 用于导入fpga的RAM存储中-How to generate mif file for importing RAM memory in fpga
create_COE_file_from_vector
- Create COE for Xilinx FPGA
FPGA_music_player
- vhdl音乐播放器，适合于FPGA，方便大家在毕业设计时使用-Music player of vhdl
_9b4ca76dcb513a53aa647a9ccf41ecb8
- 混沌的数值仿真主要包括MATLAB编程、SIMULINK模块构建、EWB仿真以及其他一些相关的软件仿真或数值计算等方法，从而获取混沌吸引子的相图、时域波形图、李氏指数、分叉图和功率谱等。混沌的硬件实验主要包括模拟/数字电路设计与硬件实验、现场可编程门阵列器件（FPGA）、数字信号处理器（DSP）等硬件实现方法来产生混沌信号。本节仅对各种数值仿真方法作简单介绍。-
Display-a-heart-shape-code
- Display a heart shape code点阵显示爱心形的FPGA Verilog 代码-Display a heart shape code
Key-and-digital-tube-display
- 按键和数码管显示，FPGA的verilog代码-Key and digital tube display
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
Division-of-digital-tube-display
- 除法器数码管显示，FPGA的verilog代码-Division of digital tube display
Adder-digital-tube-display
- 加法器数码管显示，FPGA的verilog代码-Adder digital tube display
svd_simple
- 介绍了一种简化的SVD分解算法，这个算法已在MATLAB上验证，可以用于fpga上实现-ntroduces a simplified SVD decomposition algorithm, this algorithm has been validated in MATLAB can be used to achieve the fpga
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
RS-deRS
- 总体设计RS编码解码方案，分析各种RS编码方式，并在FPGA上实现，证明设计可行性。-The overall design of RS encoding and decoding schemes, analysis of various RS encoding and implemented on the FPGA, to prove the feasibility of the design.
day8_alu_design
- this verilog code for designing ALU in fpga.-this is verilog code for designing ALU in fpga.
the signal processing technology in the software GPS receiver
- The software receiver is a type of the GPS receiver based on software written on programmable circuits such as DSP or FPGA. Based on the flexibility of software, we can integrate many techniques, update new technologies and modify its parameters when
Matlab-Code
- The software receiver is a type of the GPS receiver based on software written on programmable circuits such as DSP or FPGA. Based on the flexibility of software, we can integrate many techniques, update new technologies and modify its parameters when
ARMPFPGA-JTAG
- ARM+FPGA JTAG(二合一)原理图与PCB-ARM+ FPGA JTAG (combined) schematic and PCB