搜索资源列表
sine
- 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能,且数据ROM 在高速条件下,占用最少的逻辑资源,设计流程最便捷,波形数据获最方便。下图是此信号发生器结构图,顶层文件SINGT.VHD 在FPGA 中实现,包含2 个部分:ROM 的地址信号发生器,由5 位计数器担任,和正弦数据ROM,拒此,ROM由LPM_ROM模块构成能达到最优设计,LPM_ROM底层是FPGA中的EAB或ESB等。
DDS-16bit
- Simulation of direct digital synthesis sine wave in the MathCAD (10 bit ADC, 16-bit accumulator, 12-bit ROM, the clock frequency of 25MHz)
cpp123
- 定义一个钟表类,包括三个私有成员,分别为小时、分钟、秒,在此基础上,请重载自增运算符(++)和自减运算符(--)为类的成员函数,使得钟表类的对象能进行基于秒数的时间变化。-Defines a clock class, including three private members, hours, minutes, seconds, respectively, on this basis, overload the auto increment operator (++) and decremen
CalendarTable
- 非常好的时钟实现数据集,对于做学习matlab编程非常有帮助,而且可以放在桌面上使用,随时给你时间的提醒,希望对你有帮助。-Very nice clock for data collection, for doing very helpful to learn matlab programming, and can be used on the desktop, ready to give you time reminder, I hope to help you.
105-1602-DS1302
- 105-1602液晶显示DS1302时钟-105-1602 LCD DS1302 clock
airport
- 【问题描述】假设机场有一条跑道,每架飞机需花费一定时间着陆,花费一定时间起飞,飞机的起降满足一定的概率。一般来讲,机场存在两个队列,一个等待着陆的飞机队列和一个等待起飞的飞机队列,同样等待时间下,等待着陆的飞机比准备起飞的飞机具有更高的优先级。试编写程序模拟这个机场的运行。 【基本要求】使用队列或优先队列实现;要求可以变换起飞和着陆频率来模拟一天中的飞行高峰期和空闲期;要求可以改变着陆和起飞时间以模拟不同的效果。 【实现提示】可以假设有一个每次前进一分钟的模拟时钟,对于每一分钟,产生两个
Clock
- 主要是在桌面添加窗口小部件,给开发者极大的帮忙,同时也美观了界面- Mainly in the desktop to add widgets, developers need to help, but also the beautiful interface
clcRec
- This a clock recovery matlab code. This file is using a 4-PAM signal shape and the recovery method is DD recovery method. This file is a mfile. -This is a clock recovery matlab code. This file is using a 4-PAM signal shape and the recovery method i
clcRecoveryDDmethod
- this file is implementing CLOCK recovery using DD method in matlab. This is a mfile. The signal shape is 4PAM
7777
- STM8S103K按键修改时钟(按键中断学习),一定可以用-STM8S103K buttons modify the clock (key interrupt learning), will be used
lab1
- 利用内部时钟实现24位计数的功能,10进制,无分频,verilog语言编写-The use of the internal clock function 24 counts, 10-band, no division, verilog language
4zhongyemiandiaodusuanfa
- 基于一个虚拟存储区和内存工作区,设计下述算法并计算访问命中率。 1、最佳淘汰算法(OPT) 2、先进先出的算法(FIFO) 3、最近最久未使用算法(LRU) 4、简单时钟(钟表)算法(CLOCK) 命中率=1-页面失效次数/页地址流(序列)长度 -Based on a virtual memory storage area and work area, the following algorithm design and calculate the h
path
- 两点直接绕过障碍的最短路径计算方法,vc6编写,有示意像素界面,方便初学者理解计算方法。-Two o clock direct shortest path around obstacles calculation method, vc6 preparation, a signal pixel interface, easy for beginners to understand the calculation.
four-Interpolation
- 数值计算中常用的四钟插值代码,包括牛顿、拉格朗日、艾米特插值等-Numerical calculation commonly used four clock interpolation code, including Newton, Lagrange, Amit interpolation
MATLAB.RAR
- 由MATLAB设计一个低通滤波器,对它进行模拟仿真确定FIR滤波器的系数。-Designing a hours, minutes and seconds display electronic clock (23 hours 59 minutes 59 seconds). When the electronic clock should have manually school, school share function.
GoldBeter
- 生物钟Goldbeter2003模型C语言程序,运行环境Visual C-Clock Goldbeter2003 model C language program, operating environment Visual C++
aaaaa
- 某分布式部署的声纳系统共有n个独立节点构成。各节点内部均是物理同构的。各节点必须保持严格的时钟信号同步才能有效协同工作,使系统发挥作用。所有节点经由时钟信号总线连接,由其中一个节点担当主节点,它的时钟电路工作于主模式,向总线输出时钟信号;其余节点均应担当从节点,节点内部时钟电路工作于从模式,仅从总线获取信号,不向总线输出信号。该程序模拟了系统的可靠性和可用性-Distributed deployment of a sonar system there are n independent node
Delay_locked_lopp
- DLL可以产生精确的延迟效果而不受环境和工艺条件的影响 ,因而常用来生成稳定的延迟或多相位的时钟信号。-Effect of DLL can produce accurate delay which is not affected by the environment and conditions, so it is used to generate clock signal is delayed or more stable phase.
BSample
- BSAMPLE插值,可以用在轨道插值,钟差拟合等场合,效果不错,有需要的可以借鉴-BSAMPLE interpolation, interpolation can be used in orbit, clock error fitting and so on occasion, effect is good, need to draw upon
Newtonforward
- NETONBACK插值,可以用在GPS轨道拟合和钟差内插,可以解决runge问题,有兴趣的可以参考-NETONBACK interpolation, which can be used in GPS orbit fitting and clock difference interpolation, can solve the problem of runge, interested can refer to