搜索资源列表
cdma2k_ddc_12_1
- matlab simulink 开发的CDMA2K DDC数字下变频器和滤波器，使用XILINX FPGA V5系列，并包含DDC每个阶段的输出验证matlab程序，非常实用。-matlab simulink developed CDMA2K DDC digital down converter and filter, using the XILINX FPGA V5 series, and contains the output of each stage of verification DD
makecoe
- matlab生成*.COE文件，用于xilinx公司FPGA内部存储器的初始化文件-matlab generate*. COE file for xilinx FPGA internal memory company initialization file
fir_cic
- 用matlab生成xilinx FIR参数，对其FIR 核进行配置-Matlab generate xilinx FIR parameters to configure their FIR
New-Folder-(2)
- 基于matlab simulink的仿真程序 使用xilinx芯片设计的嵌入式系统-embedded system matlab simluink xilinx
aes_fifo_interface
- aes to fsl with xilinx fpga
ROM_GENERATOR
- 用matlab生成xilinx波形文件即coe文件。-Using matlab to generate the the xilinx waveform file.
FFT
- FFT的经典实现，三重循环的蝶形运算，适合于硬件实现的软件版本，在Xilinx的Vivado仿真器下编译通过-Classic implementation of FFT software version is suitable for hardware implementation in Xilinx Vivado emulator compiled by
lab2
- MAC implementation Using Xilinx System Generator for matlab
mycoe
- 线性调频信号脉冲压缩 用matlab生成coe文件以导入xilinx fpga -Chirp signal pulse compression using matlab generated COE file to import xilinx fpga
comptage-sur-un-afficheur33
- matbal file for xilinx design ISE ...compteur, bascule-matbal file for xilinx design ISE ...compteur, bascule....
CONVERT
- This scr iptconvert a image to coef values for ip core block ram generator xilinx
create_COE_file_from_vector
- Create COE for Xilinx FPGA
DDS
- 直接数字合成(DSS)的matlab仿真,采用simulink和Xilinx的system generator工具开发-simulink for DSS, the development tool is the system generator by Xilinx and simulink
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
proda_FixPt_xsgbbxcfg
- Fixed point xilinx system generator black box
net_fpga-2p1_051807_v15
- NETfpga 国外大学的教学源码 已经在Xilinx开发板上验证过，可行-NETfpga university
impo_these_FPGA_SAPTONO_DEBYO_00_00
- this document is a thesis discuss about fpga implementation of signal processing system on targets such as altera and xilinx
cfg_cfr_20
- 基于XILINX CFR 完整 MATLAB 产生各种带宽下的LTE CFR 系数-XILINX CFR LTE CFR PARMAETER MATLAB
pc_cfr_v3_0_msim
- 基于xilinx的cfr3.0核的仿真模型文件，对研究cfr对各种制式的信号的肖峰有不错的参考价值-The simulation model based on xilinx cfr3.0 nuclear file, studying the signal of the CFR of various formats XiaoFeng has good reference value
booth_multiplier
- A classic booth multiplier implemented using verilog HDL using the Xilinx software.