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13lab03
- 一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）-a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3)
Xilinx-FPGA-Matlab-Simulate
- Xilinx-FPGA-Matlab-Simulate.rar
filter
- 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
arithmetic
- 这是xilinx的FPGA实现各种算数运算的全部基于MATLAB的模型文件，包括加减乘除等-This is the xilinx arithmetic FPGA to achieve the full range of MATLAB-based model of documents, including multiplication and division, such as addition and subtraction
Rocket
- 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and st
XilinxFPGADesign1.1
- learn how to use Xilinx FPGA design in ten minutes
cdma2k_ddc_12_1
- matlab simulink 开发的CDMA2K DDC数字下变频器和滤波器，使用XILINX FPGA V5系列，并包含DDC每个阶段的输出验证matlab程序，非常实用。-matlab simulink developed CDMA2K DDC digital down converter and filter, using the XILINX FPGA V5 series, and contains the output of each stage of verification DD
makecoe
- matlab生成*.COE文件，用于xilinx公司FPGA内部存储器的初始化文件-matlab generate*. COE file for xilinx FPGA internal memory company initialization file
aes_fifo_interface
- aes to fsl with xilinx fpga
mycoe
- 线性调频信号脉冲压缩 用matlab生成coe文件以导入xilinx fpga -Chirp signal pulse compression using matlab generated COE file to import xilinx fpga
create_COE_file_from_vector
- Create COE for Xilinx FPGA
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
impo_these_FPGA_SAPTONO_DEBYO_00_00
- this document is a thesis discuss about fpga implementation of signal processing system on targets such as altera and xilinx
Gps-receiver-using-xilinx-fpga-and-ti-dsp-in-matl
- Gps receiver using xilinx fpga and ti dsp in matlab
源码 基于XILINX FPGA的ofdm通信系统基带设计
- verilog 源码 基于XILINX FPGA的ofdm通信系统基带设计(Experiment of digital signal processing: parallel filtering experiment code. I hope it will help.)