Verilog_黄金参考中文版,共HDL开发的朋友使用，要珍惜哦！-Gold reference Verilog_ Chinexe version of Friends of the total development of the use of HDL, it is necessary to cherish Oh!

This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p

一个CIC滤波器的源代码，基于verilog HDL语言(The source code of a CIC filter is based on Verilog HDL language.)