搜索资源列表
数字锁相环dll_code
- 通信系统中，信号捕获和同步的数字锁相环的MATLAB仿真程序-communications systems, signal acquisition and synchronization of digital PLL MATLAB simulation program
Plant
- 这些代码是用L-system语言，L-studio编译环境来实现相关功能的。主要是在实验室中的科研需要而编写的。 -these codes is L-system language, L-studio environment to compile the relevant functions. Mainly in laboratory research needs prepared.
crc_verilog
- 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
ZBT SRAM
- 用verilog HDL写的操作SRAM的源码-with Verilog HDL write operation SRAM FOSS
manchester
- 用verilog HDL实现曼彻斯特编码的源码-with Manchester Verilog HDL source code
digtalclk
- 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑
RS encoder(Verilog)
- RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
mt48lc4m16a2
- SDRAM器件mt48lc4m16.v源码，是一个功能的verilog代码。
mydds
- 数字示波器 dds...编的还不错哦。。。可以实现三种波形，而且都是用rom表-Series of digital oscilloscopes dds ... still pretty good. . . Three waveforms can be achieved, and all the table with the rom
Asynchronous_slavefifo_wr.rar
- usb-cy7c68013异步写传输代码verilog,usb-cy7c68013 asynchronous transfer write verilog code
FT3
- 此设计主要用于FT3发送编码，符合IEEE60044-8协议-This design is mainly used for FT3 to send coded in line with IEEE60044-8 agreement
cpu
- 简单的cup程序，帮助初学者学习cpu工作流程，含有仿真波形-Cup simple procedures to help beginners learn cpu workflow, containing simulated waveform
elevator
- elevaters used in transportation
neted.tar
- 一个用TCL/TK写的用于verilog的集成编辑环境.-netedit The purpose of this tool is creation of tcl/tk- based environment for convenient Verilog netlist viewing and editing. This tool will allow development of TCL scr ipts in order to make structural changes in verilog
tb_cordic
- cordic algorithm in verilog
traffic
- 交通控制灯，状态机的方式现实，分为AB2个路口-Traffic control lights, realistic way state machine is divided into junctions AB2
led
- LED Displayer是由4组7段显示器所组成,七段显示器的每一段LED相互 接 在一起,另外还各有一支common pin 接至其中一组七段显示器。
lcd_my
- 用于驱动12864lcd的Verilog语言-The Verilog language used to drive 12864lcd
fft_test
- sram controler is for you
sigmadelta_verilog_code
- sigma delta verilog code and testbench for you to do simulation