搜索资源列表
MUTIPLIER_16
- 16位乘法器的工程，用xilinx ISE设计，供初学者学习-16 multiplier works, the ISE xilinx design, for beginners to learn
multiplier_interface
- verilog 写的工程，是个基于流水线的乘法器-verilog write the works, is based on a pipelined multiplier
demo11-mlt1_vhdl
- 乘法器实验,按动S3,S4,S5,S6按键，可以将S3,S4,S5,S6相乘的结果在LED上显示-Multipliers experiments press S3, S4, S5, S6 keys, can be S3, S4, S5, S6 is the result of multiplying the LED display
multi16
- 有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。-Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace t
MULTI4BIT
- 4位乘法器由于所使用的软件是ISE，没有LPM_ROM可以直接调用，所以此设计直接调用的乘法器的IP核来完成此功能，达到同样的效果。-Four multiplier
signed_mult17b_addtree-
- 实现了17乘以17的带符号位的乘法器，采用流水结构，加法树结构-relize a multiplier by using add-tree and level archtiture.
fft
- 五阶FFT滤波器设计，verolog实现，只采用乘法器，分时实现。-Fifth-order FFT filter design, verolog, using only the multiplier timeshare achieve.
Chapter-2
- 3.1加法树乘法器add_tree_mult设计实例, 3.2查找表乘法器lookup_mult设计实例. 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例 -3.1 adder tree multiplier add_tree_mult design example, 3.2 lookup table multiplier lookup_mult design examples. 3.3 Design Example 3.4 Bo
Chapter-3
- 3.1加法树乘法器add_tree_mult设计实例 3.2查找表乘法器lookup_mult设计实例 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例-3.1 adder tree multiplier add_tree_mult design example 3.2 multiplier lookup_mult lookup table design example 3.3 Design Example 3.4 Boolean mu
Chapter-5
- 5.2 16位乘法器状态机实现 5.3 交通控制灯控制设计 5.4 PCI总线目标接口状态机设计-5.2 16 5.3 multiplier state machine traffic light control design 5.4 PCI bus target interface state machine design
multi-verilog
- 乘法器。fft。 基2.蝶形运算。旋转因子-Multipliers. fft. Group 2 butterfly. Twiddle factor
Multiplier
- 4位二进制乘法器VHDL语言源文件配有中文解释-4 binary multiplier VHDL language source files with Chinese interpretation
lxy
- 一个简单形象的八位乘法器，VHDL语言汇编，在QUARTUS II 环境下运行-A simple image of eight multipliers, VHDL language compilation environment running under QUARTUS II
32bit-multiplier-verilog
- 这是一个32位乘法器，是用verilog写的，比较详细-32*32 multiplier
project
- hspice编写的4位乘法器，运用了wallace-tree的方法-hspice muler
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat
eetop.cn_Booth_mutipler_v2
- 新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现-The new 32 booth multiplier implementations
different_multiplier
- 比较了不同设计方法下的乘法器性能，给出了计算公式-Compare the performance of different design methods multiplier under the given formulas
Galois-field-GF-(q)-.
- 伽罗华域GF（q）乘法器设计在FPGA板上的应用-Galois field GF (q) application of multiplier design on the FPGA board.
cfq[1]
- 简单乘法器调制信号频谱分析，简单入门教程-Simple multiplier modulation signal spectrum analysis