搜索资源列表
div_3
- verilog 三分频器 并含仿真文件 波形-Verilog three dividers and documents containing waveform simulation
fre_division
- 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频
miaobiao
- verilog写的分频程序,可以对输入的频率分频-Verilog write the sub-frequency procedures, can the frequency of the input frequency
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
10division
- 用verilog编写的10分频程序，仿真过，是正确的-10division
frequence_20
- 20分频器，具有一定的使用价值，自己可以试试看 。-20 frequence verilog code design and test
Simplified-2-frequency-divider
- 用verilog语言编写的两个2分频小程序，通过了验证。-Two small written in Verilog language frequency divider applet, passes validation.
div5
- 用verilog描述的任意分频器，包括奇偶分频。-Any divider verilog descr iption, including the parity divide.
mydcm1
- 基于verilog的FPGA里dcm模块分频偏移程序-dcm Frequency offset
clk_generator
- 基于Verilog HDL的任意分频代码，由本人原创，可实现0.000001Hz的步进，跟网络上的大部分简单地分频不一样！-Devicetor descr ipted by Verilog，can reach 0.0000001Hz！
half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
LCD
- verilog语言lcd的描述，verilog描述五分频电路，仿真通过，短小易懂-verilog language descr iption of the lcd, verilog descr iption fifth frequency circuit simulation through, short and easy to understand
Verilog-HDL
- 本课程设计在EDA开发平台上利用Verilog HDL语言设计数控分频器电路，利用数控分频的原理设计乐曲硬件演奏电路，并定制LPM-ROM存储音乐数据，-This course is designed to take advantage of the EDA Verilog HDL language development platform NC divider circuit design, the use of CNC dividing principles music playing ha
fp_prj
- FPGA Verilog 分频程序。用于板子验证及检测功能测试非常方便 -FPGA Verilog program , use for the board analyst and test . very helpfull
分频实现
- 用verilog实现分频模块。。。。。。。。。。。。。。。。。。。。。。。。。。。。