搜索资源列表
Ch6
- 《Modelsim电子系统分析及仿真》配盘第六章，全部为verilog HDL代码-" Modelsim electronic system analysis and simulation, with the sixth chapter of the disk, all verilog HDL code
Ch7
- 《Modelsim电子系统分析及仿真》配盘第七章，全部为verilog HDL代码-The Modelsim electronic system analysis and simulation with Chapter VII of the disk, all of Verilog HDL code
control
- 用Verilog HDL 语言描述的自动转换量程频率计控制器-Automatic conversion range frequency meter controller described using Verilog HDL
IFFT
- 基于verilog HDL的FFT功能实现-Verilog HDL-based FFT functions
manchester
- Verilog HDL 曼彻斯特编解码，16位并口的曼彻斯特编解码-manchester decode and encode Verilog
8051
- 8051使用的是verilog hdl语言可供大家学习和参考！-8051 using verilog hdl language learning and reference for everyone!
clk_generator
- 基于Verilog HDL的任意分频代码，由本人原创，可实现0.000001Hz的步进，跟网络上的大部分简单地分频不一样！-Devicetor descr ipted by Verilog，can reach 0.0000001Hz！
Xilinx_PCIe_BMD
- xilinx FPGA 开发 PCIe BMD DMA的verilog HDL源码-xilinx fpga pcie Gen 1/2 bus master device---PCIe DMA with verilog HDL
sbox
- It is AES sbox implementation with verilog HDL/ it is most recently made and works well. Very easy to understand please doen load enjoy!
PWM
- 应用verilog.HDL编写的PWM波的生成程序-Generation of application of verilog.HDL to prepare PWM wave
alu16
- 16位运算器，用实例化模块链接，是采用Verilog hdl编程，是实现fpga的代码-16-bit arithmetic unit, with links to instantiate module is using Verilog hdl programming, is to achieve the fpga code
sn74181
- 4位运算器采用sn74181，是采用Verilog hdl编程，是实现fpga的代码，实现了其模块的48种功能，-4 operator uses sn74181, is the use of Verilog hdl programming, is to achieve the fpga code, achieved its module 48 kinds of functions,
8point_dit_FFT
- 8 point DIT FFT in verilog hdl 可直接使用-8 point DIT FFT in verilog hdl
exp6_Uart
- xilinx FPGA的rs232 Verilog HDL程序-xilinx FPGA的rs232 Verilog HDL
RS_232_2
- RS232串口通讯实验，verilog HDL，在quartusII开发环境下-RS232 serial communication experiment, verilog HDL, in quartusII development environment
lab4part5
- verilog HDL coding to display hexadecimal on FPGA
frequence
- verilog hdl语言编写，频率测量系统中的一个子单元-verilog hdl Language, frequency measurement system in a sub-unit
clk_gen
- this is a clock generator program by using concurrent language verilog hdl with xilinx ise.
Adder_12bit
- 带进位的12位宽超前进位加法器，可以在工程中直接调用。使用Verilog HDL编写。-A 12-bit wide carry lookahead adder with carry bit, that can be called directly in the project. Written using Verilog HDL.
PLL
- 用Verilog HDL编写的锁相环程序-Phase-locked loop program written in Verilog HDL