搜索资源列表
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
jsjktbg1_mydown0315
- xilinx ddr controler
ddr_sdr_V1_1
- ddr verilog代码,实现DDR内存控制，是一个高效率的程序
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
DDR_SPEC
- DDRSRAM 由于经常看到，经常用到，所以还是大家下载下来看看吧！-DDRSRAM often see as a result, frequently used, so we downloaded it to see!
ddrsrdram
- ddr sdram information
DDRSDRAM
- DDR SDRAM设计及调试经验总结.pdf
ddr2_device_operation_timing_diagram_may_07_1
- DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
WS17
- weighing scale with 89s52, 24c08, PT6961 DDR, ADC 5532.
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
xapp702
- 用Virtex4系列FPGA实现DDR控制器的技术介绍-With Virtex4 series FPGA to achieve DDR Controller Technology
DDR+SDRAM控制器verilog代码及中文说明文档
- DDR SDRAM控制器代码，不可多得的源代码。内附详细说明文档。
DDR2_Chinese_data
- DDR2的中文资料，对于DDR开发人员很有帮助-DDR2 Chinese data, helpful staff development for DDR
Chapter-9
- 9.1 异步FIFO设计实例 9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
ddr_sdram
- this document explain de function of ddr sdram controller
DDR-SDRAMverilog
- DDRSDRAM Verilog以及中文解释-DDRSDRAM Verilog
DM6467_ddr
- DM6467及DM6467T芯片在CCS开发环境下测试DDR通讯是否正常的源代码。-DM6467 and DM6467T test DDR code under CCS.
pmon-pci
- pmon的打印信息，有代码的初始化过程，包括TLB，DDR，等等。-pmon print infomation
nexys4-ddr_sw_demo
- The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C)