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linux-2.4.20-rtl
- 该文件是rt_linux，实现linux的实时功能-rt_linux the document is to achieve real-time functional linux
rtl
- last time when i came here to find some clock references. but most of them can not works well. so this files works well on FPGA board.-last time when i came here to find some clock references. but most of them can not works well. so this works well o
RtlVclOptimize
- Delphi RTL-VCL optimization addon. I ve used, really good job.
rl_arm_rtl_rtx_artx
- KEIL自带操作系统RTL的中文帮助文档,很全面.
speech
- 用verilog HDL实现自相关算法！ RTL级可综合代码！ 通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
OVL
- OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform
rtl_8051_asm
- C8051 rtl的汇编驱动程序，如果能看懂会给你带来很大的好处，学习的好资料.-The driver of C8051 rtl, it will bring you very big benfit if you will read it, it is very nice.
i2c_master_slave_latest[1].tar
- I2C Core VHDL RTL Source Code for Synthesis
cwdl374s
- cc386编译器源代码的最新版本，其他参照其英文说明-This package is the sources for my DOS C compiler and related tools. See license.txt and copying for licensing information See relnotes.doc for release notes use pkunzip-d to install these files These co
FastCode
- *** *** *** *** *** *** **** *** **** FastCode Libraries ********** **************************************** .. What is does .. The following library will replace the current RTL code used by your application(s) with faster and
Delphi_MDI_child_inside_a_Package
- A Delphi Package is a special type of DLL, designed only to be used by Delphi applications. If your modules are developed as packages and not as DLLs, all modules will share the same memory manager, the VCL globals like Application and Screen, the sa
FastMM-RTL
- Delphi7 FastMM RTL 补丁, 其主要目的就是重新实现一个高效、安全、稳定的内存管理器-Delphi7 FastMM RTL
ethernet_tri_mode_latest[1].tar
- ethernet_tri_mode from opencores.org inlcude rtl and testbench
rtl-sdr
- Radio RTL8123 osmr function
Borland_Delphi_7_FastMM_RTL
- Delphi7的内存优化模块,用于优化内存的管理-Borland Delphi7 FastMM RTL
divider_VERILOG
- 采用VERILOG实现硬件除法器。提供RTL代码和仿真文件。-Achieved using VERILOG hardware divider. Provide RTL code and simulation files.
C_code_RTL
- C check RTL code 實現LDPC演算法並確認 -C check RTL code to achieve LDPC algorithm and confirm
DPF.Android.Native.Components.v1.6.8
- android component rtl for delphi xe5-android component rtl for delphi xe5
RTL_Compiler_synthesis.pdf
- HOW TO SYNTHESIZE VERILOG CODE USING RTL COMPILER This tutorial explains how to synthesize a verilog code using RTL Compiler. In order to do so, let’s consider the verilog codes below.
Verilog数字系统设计
- verilog 数字系统设计 -RTL综合 测试平台与验证 的 随书光盘源程序(This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design)