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- verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值
VB219
- （2，1，9）VB译码器Verilog代码
Verilog数字系统设计教程(第2版)
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed o
verilog_parte1
- verilog primer tutorial electronica 2 galileo
VCDdecoder
- 基于GTK-wave做的verilog test bench语法解析器 解析vcd file. 俺自己写的-VCD (Value Change Dump) file is widely used in industry. A VCD file is an ASCII file, which contains header information, variable definitions and the value changes for specified variables, or
Simplified-2-frequency-divider
- 用verilog语言编写的两个2分频小程序，通过了验证。-Two small written in Verilog language frequency divider applet, passes validation.
reg_32bit
- quartus 2中使用verilog编写32位寄存器-32-bit register
counter
- This is 2-BCD numbers Counter on board Altera DE2 Code Verilog HDL (You must import DE2_pin_assignments.csv to use this code)
CooperativeCommunication
- 1. 研究空时分组码的编译码原理及算法； 2. 研究了几种不同的协作分集系统模型和协作分集协议； 3. 将空时分组码编译码器与协同通信用硬件描述语言Verilog实现，并在ISE集成环境中综合仿真，结果正确后下载到FPGA电路板上； 4. 用示波器观察输出数据是否正确，验证空时分组码协同通信的性能。 -1. Decoding Principles of space-time block codes and algorithms 2. Study several differen
Xilinx_PCIe_BMD
- xilinx FPGA 开发 PCIe BMD DMA的verilog HDL源码-xilinx fpga pcie Gen 1/2 bus master device---PCIe DMA with verilog HDL
half_clk
- 此为用Verilog编写的1/2分频器，用以将信号的频率变为原来的2被-This is written using Verilog 1/2 frequency divider for the frequency of the signal into the original two were
key
- PS2键盘协议代码 verilog，可以在ISE上跑，约束条件：NET"F50M" LOC="B8" NET"ps2_clk" LOC="R12" NET"ps2_data" LOC="P11" NET"rst" LOC="H13" NET"seg[6]" LOC="L18" NET"seg[5]" LOC="F18" NET"seg[4]" LOC="D17" NET"seg[3]" LOC="D16" NET"seg[2]" LOC="G14"
XHDL4.0.40.part2
- vhdl语言--verilog语言 转换 2-vhdl language- verilog language translation 2
multi-verilog
- 乘法器。fft。 基2.蝶形运算。旋转因子-Multipliers. fft. Group 2 butterfly. Twiddle factor
module-counter8
- 用verilog实现8为计数器频率范围20-80kHz，根据DDS原理来一个时钟计数器记一下，n=n+1，根据公式fout=（fc÷x）÷2，fout=80 fc=320，所以n≥2时，再取反，又由公式 fout=(k.fc)÷2^n，k=50hz，fout=80khz，fc=320，所以数据的位宽n≥7。 设计要求两路方波信号的相位差在0-360゜可调，可以根据延时来实现。具体的-8 is realized with verilog counter frequency range 20-8
HW-02-13210140
- Verilog code adder for add 2 16bit in parallel-adder for 16bit used to add two bits in parallel. this code in verilog languanger
SDRAM_interface
- SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a re
notes_Lecture-2
- Advance Design with Verilog HDL Lecture 2
digital-equalizer-Verilog
- 硕士论文。主要包括：1、均衡器的设计原理 2、码间串扰与均衡原理 3、自适应均衡算法，主要介绍迫零算法、LMS算法、RLS算法 4、LMS自适应均衡器的Verilog设计 5、以上算法的matlab仿真-Master thesis. The main contents are as follows: 1, the design principle of the equalizer 2, intersymbol interference (ISI) and equilibrium principl
《Verilog HDL设计与实战》配套代码（2）
- 《Verilog HDL设计与实战》配套代码 (2)("Verilog HDL design and actual combat" matching code (2))