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xx_new4
- The purpose of this lab is to introduce the concept of FSMs with a datapath, and to study the usage of more complex test benches. Also, we enforce a rudimentary design methodology by assuming that the students are part of a bigger p
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
any_div_freq
- 可以对输入时钟任意分频(整数或小数),带Quartus II 完整项目文件.-Can be arbitrary points on the input clock frequency (integer or decimal), with complete Quartus II project document.
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶
ADPCMCodec
- Project and source code for ADPCM
EP1C3_81_SCHK
- 序列检测器设计 这里面是一个完整的工程可以直接适用-Sequence detector design there is a complete project can be applied directly
8051
- 用VHDL写的一个SPI接口程，调试通过，曾多次用项目中，感非常好用，与大家分享。-Use VHDL to write an SPI interface process, debugging is passed, with the project on several occasions, the flu is very useful to share with you.
n_hui3128
- 用VHDL写的一个动态RAM读写程序，包括工程文件可直接便用，多次用项目中。-Use VHDL to write a dynamic RAM reading and writing processes, including project documents can be directly used, several projects.
vc_parmar
- Code VHDL for a project at VHDL course and other VHDL Programs
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
fft
- vhdl code and verilog code for an 128 point fft processor which has to be executed in xlinx software as needed for course project
VHDL
- 74LS161 JK触发器带清0端,项目名称为dff_JK_111 十进制计数器74LS290,项目名定为CTLS290：运算方法编写的290计数器：另一种编法LS290 不带使能端的3线8线译码器 八选一数具选择器：用CASE语句 全加器： 简单的JK触发器-74LS161 JK flip-flop with cleared end Project Name dff_JK_111 decade counter 74LS290 project name as CTLS290: and comp
NguyenAnHai_Project3_TLC
- it is project about VHDL to control trafict light.
Microblaze Alarm System - ASM
- A Alarm system writed in Assembly to use on a Microblaze VHDL project.
counter_
- VHDL源代码+工程，可改变时钟的计数器-VHDL source code+ project, can change the clock counter
New-Project.tar
- vhdl language program
MY 80c51 IP
- verilog和vhdl混写的工程 内含mc8051软核及最小系统 经测试已调通(Verilog and VHDL mixed with the project, including the mc8051 soft core and the smallest system, the test has been transferred)