SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE

testbench顾名思义就是一个测试台，它对外没有接口，所以实体部分为空，但它要对要测试的器件提供激励信号，这其实就是最简单的testbench，本文介绍了Testbench的书写-testbench name suggests is a test bed, it is no interface to the external, physical part of it is empty, but it should provide a stimulus to the device under

fifo的testbench,简单的测试文件，非常适合学习-the testbench of fifo

This is verilog code for FIR Filter with testbench availble.