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VerilogHDLshejifengpingqihe32weijishuqi
- 本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.-This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.
verilog50%
- 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the
EasyClockDivider
- 关于用触发器构建简单分频器的介绍文档，图文并茂，讲解详细-Construction on the simple flip-flop with the divider on file with illustrations to explain the details
FPGA.CPLD
- fpga cpld 常见模块设计，包括基于fpga 的全数字锁向环，基于fpga cpld 的半整数分频器的设计等，很有用-fpga cpld common module design, including fpga-based all-digital locks to the ring, Based on the semi-fpga cpld integer divider design and useful
fenpinqi
- 《分频器设计》绝对好用的EDA实验程序！已经通过测试。VHDL语言编写-"Frequency Divider" absolutely good for EDA experimental procedure! Already passed the test. VHDL language
asdf
- EDA常用计数函数VHDL程序设计,基于VHDL的交通灯设计实例&分频器
分频器
- 详细分析了各种分频器以及其算法，还有举例！
使用VHDL进行分频器设计
- 详细介绍了利用vhdl实现小数整数分数及不通占空比分频的方法
分频器VHDL语言讲解.doc
- 分频器VHDL语言讲解
encoder
- 此为介绍一光电编码器的学术论文，采用VHDL语言编写，介绍了4分频的实现。-This is the descr iption of the papers of a photoelectric encoder using VHDL language, introduced a 4-band implementation.
dividerfrequency
- 分频器，包括2分频，4分频，8分频，16分频；6分频；20分频-Divider, including two-way, 4-way, 8-way, 16 sub-frequency six-way 20 Crossover
15
- 半整数分频器的设计 请不要上传有版权争议的内容和木马病毒代码 -Half-integer divider design, please do not upload copyrighted content and controversial Trojan code
n_evendivider
- 标签： Verilog 分频器 N倍奇数分频器.(Verilog) N_odd_divider.v / Verilog module N_odd_divider (-Labels: Verilog divider divider N odd times. (Verilog) N_odd_divider.v/Verilog module N_odd_divider (
shuzipinluji
- 数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement i
jiaotongxinhaodengkongzhiqidesheji
- 本论文主要介绍了红、绿、黄三色交通信号灯较简单的数字逻辑控制电路设计及其原理。本设计方案由定时器、分频器、扭环形计数器、十进制减法器及七段显示译码器实现交通灯红、黄、绿三色的自动切换，在切换灯光颜色的同时进行时间定时状态的切换，使整个交通灯系统得以按照事先设定的定时时间顺利运转。-This paper focuses on the red, green, yellow three-color traffic signal control of the relatively simple digi
si4133-datasheet
- 该Si4133是一个单片集成电路，既执行IF和双频 RF合成为无线通信应用。在Si4133 包括三个和VCO，环路滤波器，参考和VCO分频器，相位 探测器。除法和可编程掉电设置与threewire 串行接口。-The Si4133 is a monolithic integrated circuit, both the implementation of the IF and dual-band RF synthesis for wireless comm
frequencydivider
- 计数器和分频器的PDF资料，供大家参考哈。希望对大家有用-Counter and frequency divider of the PDF information for your reference ha. Want to be useful to everyone
RTC
- RTC 实时时钟，主要用于实现长时间计时。模块包括可选8：1 分频器，一个定时器T14，及一个32 位RTC 计数器。本例程介绍RTC的DAVE配置以及KEIL的编程指导-RTC Real Time Clock, mainly used to achieve a long time. Module includes an optional 8:1 divider, a timer T14, and a 32-bit RTC counter. The routine introduction of
digitalfreq
- 由于本人没有多少很好的源码，所以只能上传目前所做项目的相关参考文献资料。资料一的内容是数字分频器的参考文献，在fpga中数字分频器用的很多，文献对于设计小数分频器有一定的参考价值。-I am not much good as the source, we can only upload now doing projects related reference materials. Information content of a digital divider references in the
A-Universal-Programmable-Dual-Divider
- 一种通用的可编程双模分频器A Universal Programmable Dual Divider-A Universal Programmable Dual Divider