搜索资源列表
VHDL
- 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。
VHDL上机手册(基于Xilinx ISE & ModelSim).doc
- VHDL上机手册(基于Xilinx ISE & ModelSim).doc
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
ISE
- 是ISE的中文教程，主要是对初学者演示和展示在XILINX的ISE集成软件环境下，如何用VHDL和原理图的方式进行设计输入，用MOdelsim方针。-ISE is a Chinese course is mainly for beginners and display presentation of the ISE in XILINX Integrated Software environment, how to use VHDL and schematic design entry way,
RAM
- 使用ISE的XST综合，综合结果使用了Block RAM，当然有时对于用到的容量很小的RAM，我们并不需要其使用Block RAM，那么只要稍微修改一下就可以综合成Distribute RAM-The use of ISE s XST synthesis, the combined result of the use of the Block RAM, it is our expectation. Of course, sometimes the capacity to use a very s
dividefreq
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
DDRIO
- Xilinx公司开发板中的一个模块，在时钟的上升和下降沿同时传输数据。使用时需要在ISE集成开发环境下利用VHDL进行例化。本文是对该模块功能的说明，是个人的学习总结-Xilinx has developed a module board, in the clock' s rising and falling at the same time transmission of data. ISE needs to use integrated development environment
lcd_controller
- LCD controller 320x240 XC95144, building Xilinx ISE 6.0 Platform VHDL.
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
DesignofFloatingPointCalculatorBasedonFPGA
- 给出系统的整体框架设计和各模块的实现，包括芯片的选择、各模块之间的时序以及控制、每个运算模块详细的工作原理和算法设计流程；通过VHDL语言编程来实现浮点数的加减、乘除和开方等基本运算功能；在Xilinx ISE环境下，对系统的主要模块进行开发设计及功能仿真，验证 了基于FPGA的浮点运算。 -The overall framework of system design and realization of each module which contain selection of ch
keypad4x4_4
- THIDS CODE VERY GOD FOR DRIVE KEYPAD4X4 IN VHDL COD IN ISE
vga_ise7_bak
- THIDS CODE VERY GOD FOR DRIVE VGA IN VHDL COD IN ISE
Assignment-3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx I
VHDL_design
- 本综合实验包括节拍脉冲发生器、键盘扫描显示和八位二进制计数器三个模块。采用VHDL语言为硬件描述语言，Xilinx ISE 10.1作为开发平台，所开发的程序通过调试运行验证，初步实现了设计目标。-This includes comprehensive experimental beats pulse generator, display and keyboard scan eight binary counter three modules. Using VHDL as the hardwar
clock____!
- The project is designed with the hour hand and the minute and the second time in the ISE software language. Vhdl written.
FIR_poroje
- this project is about FIR FIlter By VHdl codes in the ISE.
uart
- uart_reciver with vhdl (ISE Design Suite 14.7)