搜索资源列表
synopsis_FSM_coding
- synopsis的有限状态机编码方法的文档。 针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。 FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the in
fre_ctrl
- 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL descr iption of the behavior and structure of a descr iption of the realization of frequency
StateMachineCodingStylesforSynthesis
- 关于verilog编码风格的文章，写得不错，值得反复阅读。-Verilog coding style on the article, written well, it is worth reading again.
NonblockingAssignment
- 详细介绍verilog语言中的阻塞和非阻塞问题-Detailed Verilog language obstructive and non-blocking problem
pll_verilog
- verilog model of a P-verilog model of a PLL
FPGA_based_infrared_receiver_module
- 基于FPGA的红外接收模块，内含代码，采用VERILOG编写。-FPGA-based infrared receiver module, containing the code prepared by the use of Verilog.
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
verilog
- verilog的教程，对初学者很有帮助，与大家分享-the Verilog tutorial, very helpful for beginners to share with you
GPIO
- GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface-Use verilog to design a 48 control points that can be programmed to input or output controller
labQ2
- Source codes for verilog fifo for spartan 3
lab3
- verilog source code for uart design
verilog
- 这是初步学习verilog的有用资料．包括了全部的基础知识．有需要的朋友赶快来下载哦．-This is a preliminary study useful information verilog. Including all the basic knowledge. There is a need to get friends to download Oh.
4
- 双向端口verilog 代码,用于既可输入，又可输出的端口设计-verilog
planta_fagner
- is a test of a verilog implementation to do a oscilloscope with dual-port RAM
watchver
- watchdog with verilog
the_verilog_hardware_description_language_fifth_e
- the verilog hardware descr iption language
async_transmitter
- 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
i2c_verilog
- verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
Verilog
- verilog HDL语言使用手册，包括：语法规则，RTL设计思想和方案等-verilog HDL language user manual, including: grammar rules, RTL design ideas and programs
segment
- 7 segment display using verilog interfacing fpga and 7 segment display