用于RS码译码的两种新电路:普通基“比特串行序列乘法电路”和“比特串行 乘法累加电路”,基本上以m个与门代替了两个任意元素相乘的复杂乘法器,使译码电路大大简化.作为一个应用实例,详细阐明了用它们构造的RS码纠删/纠错译码各步电路. -Used for RS code of decoding two new circuit: common base "bit serial sequence multiplication circuit" and "bit serial multiplica

8位基2FFT算法的蝶形运算的代码，不含有复数乘法器-8 base 2FFT algorithm butterfly operation code does not contain a complex multiplier

this is fast complex multiplier in vhdl

Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b