Abstract—Power is becoming a precious resource in

modern VLSI design, even more so than area. This paper

proposes a novel architecture for modular, scalable &reusable

hybrid constant co-efficient multiplier (KCM) circuit.

Comparison is made between of kcm and multiplier. The

implementation results show a significant improvement in

performance in terms of area, power & timing. In This paper,

we propose to design an 8-point FFT using kcm instead of

complex multiplier and multiplier. Here our goal is to

implement Radix-2 8-point FFT in hardware using hardware

language (verilog) here time constraint is measured with the

help of Xilinx FPGA (Field Programmable Gate Array).