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DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
Verilog_shuzisheji
- 本章的目的是想通过对数字信号处理、计算（Computing）、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (
verilog
- verilog的各种编程实例 有源代码的从简单到复杂-verilog source code of various programming examples from the simple to the complex
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
FPGA-Prototyping-By-Verilog-Examples
- HDL (hardware descr iption language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical impl