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ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
week04-knn-naivebayes-4pp
- knn naivebayes ppl file
low-jitter-Clock-IC
- 每个数码系统之所以正常准确工作的基础是其心脏 – 时钟序列的无误. 而用来产生时钟信号的资源有许多种: 系统主芯片输出时钟信号, 以MCU微处理器来产生时钟, 以成本较低的晶振来产生时钟信号, 但是还是有很多人不知道或不了解我们还有另外一个选择:用一个集成电路PPL(锁相环)时钟芯片.-Each of the digital system is the reason why the normal work accurately based on the its heart- clock sequ
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- Visual C++本地并行编程中的状态管理,新的Beta1 PPL的其中一个功能就是可以取消正在运行中的任务组-Parallel programming in Visual C++ local state management, the the new Beta1 PPL which a function is to cancel the running task group
telligen-
- 本文给出了一种新型智能电子秤的设计方案。该系统以单片机作为中心控制单元, 采 用V ö F 型模数转换、锁相倍频、非线性校正和数字滤波等技术。- Th is paper p resen t s a new design fo r the in telligen t elect ron ic scale. The m icro2 con t ro ller w as u sed as the cen t ral con t ro l un it in the system , t