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17bit_Smart_Absolute_Encoder.z
- 多摩川17bit绝对值编码器的NRG协议文档，配合上传的解码源程序，采用半双工的通信模式。,Tamagawa 17bit absolute encoder NRG agreement documents, with the upload source decoder, using half-duplex communication mode.
encoder
- 此为介绍一光电编码器的学术论文，采用VHDL语言编写，介绍了4分频的实现。-This is the descr iption of the papers of a photoelectric encoder using VHDL language, introduced a 4-band implementation.
Manchester
- “Manchester码（双相码）编码器- Manchester Code (two-phase code) encoder
rsenc
- this the code for reed solomon encoder of type 7,3. this is the main module program.-this is the code for reed solomon encoder of type 7,3. this is the main module program.
mult2
- this the multiplier 2 module for the reed solomon encoder-this is the multiplier 2 module for the reed solomon encoder
mult4
- this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder
mpeg
- mpeg encoder and decoder
FPGA-basedincrementalphotoelectricencodercountcirc
- 基于FPGA的增量式光电编码器计数电路设计,文章含有Verileg HDL代码.-FPGA-based incremental photoelectric encoder count circuit design, the article contains Verileg HDL code.
8b10b_encdec
- 8b/10b encoder/decoder vhdl source-8b/10b encoder/decoder vhdl source
mkjpeg_latest
- jpeg encoder vhdl source code
generate_trellis_rsc_c
- vhdl code for convolutional encoder
RS3123
- Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its ra
robotic_arm
- An effort has been made to design a robot, which loads and unloads an object to the station depending on the request. The sensor connected to the robot will sense the request and initiate the correct sequence of operation. The robot under design has
ENDAT2.2-Code
- 海德汉绝对式编码器代码，VHDL语言编写-Heidenhain absolute encoder code, VHDL language
FPGA_Project
- To design fixed point to floating point encoder and experiment with simulation, synthesis and implementation features of the Xilinx Project navigator. Specifically, the objectives of this lab are: 1. To try out basic building blocks of VHDL beh
PRIORITY-ENCODER
- this the vhdl code fot 4:2 priority encoder-this is the vhdl code fot 4:2 priority encoder
mux21a
- 基于FPGA的用VHdl硬件语言实现的双二选一编码器。-Choose an encoder FPGA-based hardware with VHdl language of bis.
Convolutional-encoder-VHDL-code-_-VHDL-Programmin
- convolutional encoder in vhdl