文件名称:FPGA_Project
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- 上传时间：2013-01-02
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文件大小：16.65kb
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To design fixed point to floating point encoder and experiment with
simulation, synthesis and implementation features of the Xilinx Project navigator.
Specifically, the objectives of this lab are:
1. To try out basic building blocks of VHDL behavioral descr iption especially
processes.
2. To learn how to translate problem specification into VHDL code.
3. To consolidate understanding of the development board and to learn different
techniques of utilizing its resources.
4. To consolidate test bench writing skills.
simulation, synthesis and implementation features of the Xilinx Project navigator.
Specifically, the objectives of this lab are:
1. To try out basic building blocks of VHDL behavioral descr iption especially
processes.
2. To learn how to translate problem specification into VHDL code.
3. To consolidate understanding of the development board and to learn different
techniques of utilizing its resources.
4. To consolidate test bench writing skills.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_Project/cg.vhd
FPGA_Project/counter.vhd
FPGA_Project/font_unit.vhd
FPGA_Project/s.vhd
FPGA_Project/text.vhd
FPGA_Project/top.ucf
FPGA_Project/top.vhd
FPGA_Project/vga.vhd
FPGA_Project/vga_counter.bit
FPGA_Project
FPGA_Project/counter.vhd
FPGA_Project/font_unit.vhd
FPGA_Project/s.vhd
FPGA_Project/text.vhd
FPGA_Project/top.ucf
FPGA_Project/top.vhd
FPGA_Project/vga.vhd
FPGA_Project/vga_counter.bit
FPGA_Project
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