搜索资源列表
60711869-Mac
- MAC design in vlsi for dsp application
Wave-Pipelining-A-Tutorial-and-Research-survey.zi
- Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The combination of high-performance integrated circuit (IC) technologies, pipelined arch
verilog-FAQ
- Low power SRAMs have become a critical component of many VLSI chips. This is true for microprocessors, where on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and main memory. Simu
EE5301-Plc
- related to cad for vlsi systems in todays systems
09_TESTINGINTRO
- vlsi testing in front end and back end-vlsi testing in front end and back end
test.in
- introduction to vlsi testing
01Intro0602
- VLSI Testing and Design for Testability
hcsa-2
- Hcsa adder in vlsi subject in vhdl
ALU_exercise
- 弗莱堡大学VLSI课程ALU练习，希望对大家有帮助-University of Freiburg VLSI courses ALU practice, we hope to help
tieu-luan-VLSI_huept_27042013
- Clock in design VLSI
VLSI5
- vlsi papers low power area
ieee-(4)
- Network on chip is an emerging[when?] paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip
VLSI_NEW_AUTHOR
- Enable vlsi book for any electronics vlsi enginerrEnable vlsi book for any electronics vlsi engine-Enable vlsi book for any electronics vlsi enginerrEnable vlsi book for any electronics vlsi enginerr
code
- matlab code for speech in vlsi
Resume
- arm vlsi verilog vhdl embedded
PART_V
- vlsi related document delete if copyrighted
Planar-integrated-optical-vector-matrix-multiplie
- We present the design of a planar-integrated optoelectronic vector-matrix multiplier. The inherent parallel-processing potential is fully exploited by optical implementation of multiplications and summations. Planar integration makes the free-spa
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
ieee
- VLSI Implementation IEEE Papers 2010 to 2014
2009_07_ofdm_chn
- VLSI Implementation of OFDM Channel Estimation.