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sha1_v01
- sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equa
thesis
- thesis for simple virus detection processor which is developed in xilinx
library-IEEE
- pid controller design for implementation in xilinx for controlling dc motor speed using feedback which is obtained through optical sensor -pid controller design for implementation in xilinx for controlling dc motor speed using feedback which is obta
Tutorial_virtex7
- This a simple chip test program for Xilinx Virtex7. -This is a simple chip test program for Xilinx Virtex7.
ISE_TOOL_FLOW
- This Document Perhaps is the Xilinx Work flow under the Xilinx Environment FPGA Architecture
DSP-with-FPGAs
- Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago. Many front-end digital signal processing (DSP) algo
axi-timer
- 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值 -The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface.
coolrunner-ii_sch
- 基于CPLD的XILINX的系统设计，很适合初学者参考。-XILINX CPLD-based system design, it is suitable for beginners reference.