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pacman_rel004_sp3e
- altera,de2,cyclon11,tetris, project
SHA-1ImplementationOnFPGA
- 希算法SHA-1算法广泛地应用于电子商务、商用加密软件等信息安全领域。通过对SHA．1算法的深入 分析，提出了流水线结构的硬件实现方案。通过缩短关键路径，使用片内RAM代替LE寄存器实现流水线中间变量 的数据传递，有效地提高了工作频率和单位SHA-1算法的计算速度。这种硬件结构在Altera系列芯片上的实现性能 是Ahera商用SHA-1算法IP核的3倍以上。-Hash algorithm SHA-1 is used widely in cryptographic applicati
EP3C25Pin-Outs
- altera公司的可编程逻辑门阵列FPGA，引脚详细信息尽在于此，对pcb的绘制活原理图的设计非常有帮助-altera programmable logic gate array FPGA pin Details do in this very helpful, drawn live on the pcb schematic design
crack
- altera公司的破解器，从6.0版本的quartsii到11.1版本的-altera company' s cracker, from 6.0 to 11.1 version of quartsii
coding_style
- 神州龙芯的codingstyle,包括一些书写规范及其他的编码风格适合刚入门FPGA的同学，骏龙是altera中国的代理商，-BLX s codingstyle, including some writing specifications and other FPGA coding style suitable for students just getting started, Cytech is altera China s agents,
FPGA_ENVIRONMENT_BUILD
- FPGA环境的搭建，安装altera qaurtus ii 11.1和modelsim 6.5d se 图形化简单实用。-FPGA environment to build, install altera qaurtus ii 11.1 and modelsim 6.5d se graphically simple and practical.
precision-frequency-meter-design
- 基于51软IP核的等精度频率计设计，利用altera提供的软51ip核，用VHDL语言实现的-Based on 51 soft IP cores, such as precision frequency meter design, the use of the software provided 51ip altera core, using VHDL language
FFTPVerilog
- FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
Qsys_altera
- altera的quartusII中，最好的qsys入门学习资料-altera' s quartusII, the best qsys learning materials
yinpinxinhaofenxiyi1233412
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核的基于FFT的音频信号分析仪-Based on Altera Cyclone II series FPGA embedded high-performance embedded IP core (Nios) soft core processor FFT-based audio signal analyzer
an374_altera_IP
- The Altera® Video Over IP Reference Design implements a system that bridges between MPEG transport stream (TS) data and Ethernet-based internet protocol (IP) networks.-The Altera® Video Over IP Reference Design implements a system that b
FINAL-LAB04
- VHDL Software (Altera DE2 board) that works as a Hotel Safe Box. When in the open state it will store a combination of 6 inputs between 0 to 3, then it will stay closed until the correct input is placed. -VHDL Software (Altera DE2 board) that works a
Cyclone_III
- 详细讲述Altera FPGA Cyclone_III的配置-Details about Cyclone_III configuration
the-digital-clock
- 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自 顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测 试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐 闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of ALTERA. And with the help of VHDL, the de
The-Phase-Locked-Demodulation-
- 利用Altera公司推出的FPGA开发工具DSP Builder，对锁相解调算法中的主要部件：数控振荡器(NCO)、计算反正切的CORDIC模块和FIR低通滤波器进行了单独设计和仿真，最终完成了锁相解调系统的整体设计。-Designed and simulated major components of phase-locking Demodulation Algorithm independently, including: Number Controlled Oscillator(NCO)、
br-soc-fpga
- cyclone v的altera公司的带arm硬核的soc设计指南-cyclone v the product of altera with the arm hard process cores introductiong
license11
- best license crack for all altera quartus -best license crack for all altera quartus
DisplayPort_TX-Only_Desgin_Example_AN
- ALTERA displayPort TX reference design 1920x1080
ss-single-chip-4k-upscaling
- 4K upscaling ALTERA FPGA verilog
ug_ddr_ddr2_sdram_hp
- ALTERA DDR2高性能控制器使用文档，包括存储控制器、用户接口、用户测试模块，各控制信号的说明。-ALTERA DDR2 high performance controller using a document, including the memory controller, user interface, user testing module, the control signal descr iption.