搜索资源列表
DividerSLV
- VHDL source code for combinational divider with standard_logic_vector types
DividerSLVcompact
- VHDL source code for combinational divider with standard_logic_vector types, more compact version with lower resources requirement
power_divider_based_ADS_simulation
- 这是一个基于ADS的功分器制作的PPT，从理论到实践仿真，比较全面，以供参考。-power divider based ADS simulation.
lem
- 用分压器测量30～300Hz交流电压时的问题Measured with a voltage divider 30 ~ 300Hz AC voltage problem-Measured with a voltage divider 30 ~ 300Hz AC voltage problem
134946
- The CS5460A is a highly integrated power measurement solution which combines two Analog-to-digital Converters (ADCs), high-speed power calculation functions, and a serial interface on a single chip. It is designed to accurate
23824648pinlvji
- 1. 测量信号:方波 ； 2. 测量频率范围: 1Hz~9999Hz 3. 显示方式: 4位十进制数显示 4. 时基电路由 555 定时器及分频器组成, 555 振荡器产生脉冲信号,经分频器分频产生的时基信号,其脉冲宽度分别为: 1s, 0.1s 5. 当被测信号的频率超出测量范围时,报警. -Measuring signal: square wave measurement frequency range: 1Hz ~ 9999Hz display: four d
VHDL-divider
- 8位数除法器，用的软件是quartus，被除数是8位的，除数4位-8-digit division, software quartus dividend is 8, the divisor 4
COP2000-experimental-instrument
- 计算机组成原理 利用COP2000实验仪自行设计指令系统实现乘法器和除法器实验指导-Principles of Computer Organization the use of COP2000 experimental instrument design their own instruction set multiplier and divider experimental guidance
2
- 关于FPGA的分频代码,是vhdl语言编写的，可能比较简单，但比较实用。-Divider code on the FPGA
EDA
- 基于 CPLD/FPGA用原理图和VHDL语言混合设计实现了一多功能通用分频器。-CPLD/FPGA-based mixed schematic and VHDL language design and implementation of a multi-function universal divider.
Clk_Divider
- System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
seq_div
- 除法器设计 样例程序-Divider design sample program
Masseffect-3---Jane-Shepard
- 超級好用 25M~100HZ的除頻器 寫了好久 超級實用 歡迎下載-Super easy to 25M ~ 100HZ of divider wrote a long time super practical welcome to download
wang
- vhdl语言的四位二进制除法器，带有详细的流程图及计算原理-vhdl language of four binary divider, with a detailed flow chart and calculation principles
div_clk17
- 手写时中分频，17分频，用状态机写成，之欧诺个两个过程语句简单明了易懂-Handwritten carve frequency divider 17, the state machine languages, the two processes Uno a statement, jianji8e clear and understandable
001
- 分频器的四连体数码管显示源代码以及对其分析-The four-piece divider digital display source code and its analysis
zhen1
- 本文设计的数字分接器是由帧同步提取模块、位同步提取模块、帧同步移位和时序信号恢复模块、分路器模块、串/并转换电路模块五部分组成-Digital tapping machine is designed in this paper by the frame synchronization extraction module, a synchronous extraction module, the displacement of frame synchronization and timing si
fec_code
- The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by four, but the divide value can be chan
egprog
- EG8010 is a digital pure sine wave inverter ASIC (Application Specific Integrated Circuit) with complete function of built-in dead time control. It applies to DC-DC-AC two stage power converter system or DC-AC single stage low power frequency tra
clk_divR
- frequency divider into reglable frequence