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pld MegaWizard Plug-In Manager
- 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_
Verilog
- 是摩托罗拉关于Verilog HDL的开发规范，相信对于学习Verilog程序设计的人会有很大的帮助-Motorola on the development of Verilog HDL specification, I believe that learning Verilog for programming will be of great help to people
dds
- 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
GPIO
- GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface-Use verilog to design a 48 control points that can be programmed to input or output controller
ddc
- 随着数模转换器硬件的快速发展和DSP处理能力及处理速度的逐步提高，软件无线电技术在商用和军用无线电通信领域也越来越显示出其强大的吸引力。本文研究的高速中频采样和数字下变频技术是目前蓬勃发展的软件无线电领域的两项关键技术。-As advances in technology provide increasingly faster and less expensive digital hardware, more of the traditionally analog functions of a
avs_export
- the avalon verilog slave sram interface fron be micron
VerilogCh4
- VHDL and Verilog code referrals tools, EDA staff to be very helpful. vend machine
DirectX_Updater
- Do I HAVE to backannotate to use these models? No but, to ensure correct results, you must pass the correct values to the models s generics. This can be done by editing the model s instantiations in your netlist. SDF backannotation may be easier
liyamin_slides
- 基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用AHDL编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and user manual,
PLL(pdf)
- 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
CHU92A
- MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
pal.rar
- PAL制式时序发生verilog模块，13.5MHz，频率可以改,PAL video timing generator verilog modules, 13.5MHz, the frequency can be changed
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
verilog
- 用verilog设计的存储器，可以读入数据，读出数据，是集成电路重要运用单元-Design with verilog memory that can be read into the data, read data is important IC with Cell
ADC_16bit.v
- 一个verilog编写的16位ADC程序。该程序方便了DAC的设计人员对DAC提供输入信号，以此可以获得理想的DAC所需信号-Verilog to write a 16-bit ADC program. The program facilitates the DAC' s designers to provide input signals to the DAC, in order to be able to get a good DAC desired signal
key_duli
- FPGA实现verilog语言的按键防抖功能，能够很有效的实现了按键的加减数据的功能，通过一位数码管显示。-FPGA implementation verilog language button image stabilization feature, can be very effective to achieve the subtraction key data features, through a digital display.
Verilog-VGA
- 用于FPGA的实验的字符显示，实验程序所用，可以作为参考。-Character for FPGA experiments show that the experimental procedures used, can be used as a reference.
Verilog
- Verilog课程设计自动售货机 1）设计一个自动售货机，此机能出售1.5元、2元两种商品。出售哪种商品可有顾客按动相应的一个按键即可，并同时用数码管显示出此商品的价格。可同时购买两种、多件商品。 2）顾客投入硬币的钱数有5角、1元两种。此操作通过按动相应的两个按键来模拟，并同时用数码管将投币额显示出来。 3）顾客投币后，按一次确认键，如果投币额不足时则报警灯亮。如果投币额足够时自动送出货物（送出的货物用相应不同的指示灯显示来模拟），同时多余的钱应找回，找回的钱数用数码管
verilog-a-lrm-1-0
- The information contained in this draft manual represents the definition of the Verilog-A hardware descr iption language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranties whatsoever with respect t
FPGA-Prototyping-By-Verilog-Examples
- HDL (hardware descr iption language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical impl