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17bit_Smart_Absolute_Encoder.z
- 多摩川17bit绝对值编码器的NRG协议文档，配合上传的解码源程序，采用半双工的通信模式。,Tamagawa 17bit absolute encoder NRG agreement documents, with the upload source decoder, using half-duplex communication mode.
-VHDL
- 本报告分两部分： 1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 -FIR digital filters based on VHDL
or_gate1
- 入门知识：或门用VHDL语言如何描述，并正确掌握VHDL语言的规范写法-Started: VHDL language or how to describe the door, and the right to master the VHDL language specification writing
VHDLorverilogHDL
- 选择VHDL还是verilog HDL，说明文档-Choice of VHDL or verilog HDL, documentation
Manchester
- “Manchester码（双相码）编码器- Manchester Code (two-phase code) encoder
chuzuchejifeiqi
- 出租车计费器 课程设计报告 详细介绍其工作原理及工作过程-Taxi meter course design report details of its working principle and working process
vhdl
- 电梯控制器的模块电路，其中一个很重要的模块，是txt格式的代码-Elevator controller module circuit, which is a very important module is the code txt format
LVDS
- 很多液晶屏都具有LVDS接口，本文对液晶屏的各种LVDS接口定义进行了详细说明。-Have a lot of LCD LVDS interface, this article on the various LVDS LCD interface definition described in detail.
AD_TLC5510
- 用VHDL控制TLC5510从而实现对高速A/D器件TLC5510控制，进而处理-use fpga to control the tlc5510
VHDL
- eda课程，包括数码管显示，可变步长计数器的编写-eda courses, including digital display, variable-step preparation of counter
vhdl
- 找到的一个自动售货机的vhdl程序，关于eda的设计有没有最新的一些说明之类的饿-The vendor 1 of source code ． vendor can sell 3 kinds of merchandise: The Hamburg and 1 Yuan of hot dog wrap 2 Yuan and double-deck Hamburg 3 Yuan. It is infinite to set up quantity. 2 ． vendor promise input 1
VHDL
- 非常有用的资料，对学习VHDL很有帮助，大家要好好珍惜-Very useful information, to learn VHDL helpful, we have to cherish! !
pp
- ANN VHDL Implemenetataion
VHDL
- 的应用实例 很有哟 针对爱好者可以联系我-vhdl
lunwen
- 利用VHDL设计的电梯系统毕业论文，包括所有波形和管脚分配-The elevator system design using VHDL thesis, including the distribution of all waveforms and pins
VHDL
- VHDL相关的知识，说明了在学习VHDL过程中长出现的一下问题，是很好的材料。-VHDL knowledge, long learning VHDL process of what is a very good material.
数字信号处理的FPGA的实验的VHDL编码
- 数字信号处理的FPGA的实验的VHDL编码-Experiments of the digital signal processing FPGA VHDL Code
vhdl-tutorial
- The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It i
vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）--Design of VHDL algorithm for pseudo random sequence generator is a pseudorandom sequence generator, using the generating polynomial 1+X^3+X^7. RESET has a cli
VHDL-sequence-detector
- VHDL 序列检测 对特定的序列进行检测-VHDL sequence detector