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-VHDL
- 本报告分两部分： 1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 -FIR digital filters based on VHDL
61EDA_D462
- 用MATLAB生成mif and hex（QUARTUS II）内存初始化文件简介-Using MATLAB to generate mif and hex (QUARTUS II) Memory initialization file About
QUARTUS_II_compile_and_simulate
- Verilog HDL 在QUARTUS II下的编译和仿真顺序-Verilog HDL in QUARTUS II compiler and simulation under the order of
Quartus
- Quartus II 是Altara公司继MAX II之后开发的新软件，很适合做FPGA的开发。-Quartus II is Altara after the company following the MAX II development of new software, it is suitable for FPGA development.
Quartus-II--Handbook-Version-11.0
- Quartus II 技术手册，详细说明quartus使用时注意事项-Quartus II Handbook Version 11.0
基于FPGA直接序列扩频系统的设计
- 针对一般无线通信系统抗干扰、抗噪声以及抗多径性能力差的缺点，提出了一种基于FPGA 的直接序列 扩频系统设计。该设计采用63 位的pn 码作为扩频调制的码序列，在发送端，对信息码进行扩频调制; 在接收端，对 收到的扩频调制信号进行解扩，增强了系统的抗干扰性和可靠性。同时在Altera 公司的Quartus II 软件中，使用硬件描 述语言VHDL 和原理图相结合的方法进行了电路的设计实现。通过把电路下载到Altera 公司的CycloneIII 的 EP3C10E144C8N 芯片中调试
text_FPGA
- 以例子的方式介绍如何使用quartus ii，快速有效，是一个很好的fpga的入门资料-y way of example how to use quartus ii, fast and effective, is a good introductory information fpga
ug_ram_rom
- This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP c
qts_qii52002
- FPGA design software that easily integrates into your design flow saves time and improves productivity. The Altera® Quartus® II software provides you with a command-line executable for each step of the FPGA design flow to make the design
hardwired
- 掌握硬连线控制器的设计方法。掌握硬连线控制器的Verilog HDL描述方法。了解QUARTUS II硬件描述语言和原理图混合输入设计的过程。 -Master the design method of hard wired controller. Grasp the hard wired controller Verilog HDL descr iption method. To understand the process of QUARTUS II hardware descr ipti
AES-FPGA
- 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA