本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by

using different architecture of mixcolumn. We then review this research investigates the AES algorithm in

FPGA and the Very High Speed Integrated Circuit Hardware Descr iption language (VHDL). Altera

Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of

transformations of both Encryptions and decryption are simulated using an iterative design approach in

order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware　uation.