搜索资源列表
fr_div
- DDS divider clock AHDL
DDS_IP
- Document for DDS implementation in FPGA It generates Freq upto 240 KHz
signal-generator-design
- 基于DDS技术的信号发生器设计，能产生正弦波，方波，三角波。-The signal generator design based on DDS technology, which can produce sine, square, triangle wave.