搜索资源列表
CRC
- 详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其算法实 现。-Details of Cyclic Redundancy Check CRC (Cyclic Redundancy Check) theory and the error control algorithm.
RS_decode
- RS编译码算法的实现 RS 码以其强大的纠突发错能力, 被广泛应用于各种差错控制场合。本文讨论了RS 码的编码和译码算 法及其软件实现。-Implementation of RS encoding and decoding algorithm for RS codes with its powerful burst error correcting capabilities, error control is widely used in various occasions. This
crc_explain
- 循环冗余校验 CRC 的算法分析和程序实现。通信的目的是要把信息及时可靠地传送给对方，因此要求一个通信系统传输消息必须可靠与快速，在数字通信系统中可靠与快速往往是一对矛盾。为了解决可靠性，通信系统都采用了差错控制。本文详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其算法实现-Cyclic Redundancy Check
verilog_hdl_huawei
- 华为verilog，vhdl入门资料。内容浅显易懂，不可多得的好资料。-Huawei verilog, vhdl introductory information. Content easy to understand, rare good information.
verilog_dpll_
- 该源代码是用FPGA实现数字锁相环的逻辑，有需要的可以借鉴参考一下。-The source code is to use FPGA implementation of digital phase-locked loop logic, those in need can draw reference.
564-784-fpga-1-develop
- 该文档主要针对Verilog语言的快速应用指南，包括语法、综合及硬件方面的应用等内容-The document aimed at the rapid application of Verilog language guide, including grammar, comprehensive and content of the application of hardware
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
DesignCompilerPPT
- 用design compiler对verilog hdl的程序进行逻辑综合最后生成门级网表即用门生成的电路图。-Verilog hdl with design compiler of the logic synthesis procedure generates the final gate-level netlist that is generated with the door circuit.
csa
- This common interview question ask about verilog-This is common interview question ask about verilog
mux_case
- 用case 语句描述的4 选1 MUX源代码程序实现-case4（1） ，VHDL&verilog
traffic
- 绿灯、黄灯和红灯交通指示灯的verilog HDL程序源代码-traffic lamp ，red,yellow,green,verilog HDL
clock
- 多功能数字钟的Verilog ＨＤＬ源代码程序的实现-ｍｕｔｉｌ－ｆｕｎｃｔｉｏｎ ｄｉｇｉｔａｌ ｃｌｏｃｋ Verilog ＨＤＬ
phy_congfig
- 88e1111的寄存器的控制，使用verilog，已经调试通过,能够对88e1111操作。-The 88E1111 register control, use verilog, and has been through debugging.
chapter9
- 一个别人写的ＵＡＲＴ ｖｅｒｉｌｏｇ程序，希望对大家有帮助-A UART verilog program written by someone else, we want to help
tse_ref_design
- altera 三速以太网参考设计，verilog源码-Triple Speed Ethernet Data Path Reference Design
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
SerialPort_RxTx
- verilog 简单易用，占用资源少。 串口收发模块。-verilog .Serial port receive & transmition module
juanjima
- 231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创-Verilog achieve 231 convolutional code, preceded by a detailed descr iption of the document, the source, the absolute originality! ! ! !
Verilog_HDL_basics_online_CN
- 是一本比较精炼但是很全面的Verilog语言教程-Is a more refined but very comprehensive Verilog language tutorial
yinjianmiaoshuyuyanVerilog(disiban)
- 这是硬件描述语言verilog的第四版，希望对大家的学习有帮助。-This is a hardware descr iption language Verilog fourth edition, I hope to learn from everyone.