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jiaozhi
- 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。 -Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
DE1_SD_Card_Audio
- an project of sd card codec on verilog from altera
Verilog_HDLsequence-generator
- Verilog序列产生器，内有代码，可产生随机序列-Verilog sequence generator, which have code that generates random sequences
VerilogHDL_build_module_v4
- Verilog基础文档，跟着例程跑完，收获绝对相当大！-Verilog base document, followed by routine finish, harvest absolutely quite large!
shixunlaozhong
- 基于Verilog HDL语言的多功能数字钟，能够实现置位和清零功能。 -Verilog HDL language-based multi-function digital clock, to achieve set and clear functions.
latch
- Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made b
renmin331
- FPJA Verilog序列检测器1001 -1001 Sequence Detector
mysunrom
- FPJA的verilog 正弦信号发生器-sinusoidal signal generator verilog
jishuqi
- 4位二进制的计数器 Verilog 代码-4-bit binary counter Verilog code
Verilog
- 夏宇闻数字逻辑设计，非常好的VHDL学习资料，不多说了-Xia Wen digital logic design, VHDL very good learning materials, not much to say
14_Lab6
- filter desing using verilog code using matlab
12_Lab3
- practical example using verilog and vhdl by xilinx
LFSR
- practical example using verilog and vhdl by xilinx
DEMUX
- practical example using verilog and vhdl by xilinx
Animation
- practical example using verilog and vhdl by xilinx
dianzhen
- 点阵图形显示，十字和叉字循环显示，利用verilog语言汇编，有测试代码。-Dot matrix graphic display, cross and cross word cycle display, using Verilog language, assembly, testing code.
convolution
- convolution codes using verilog language for FPGA
zhongzhilvbo
- 中值滤波的ＦＰＧＡ（Verilog语言）实现方法，可以作为通信，图像专业的编程参考， -Median filter FPGA (Verilog language) implementation can be used as communication, professional programming reference image,
router
- router design in verilog
_Verilog_HDL-study
- 对Verilog hdl语法学习有较大帮助 适合新手学习-Learning grammar for Verilog hdl great help for novices to learn