搜索资源列表
lfsr6s3
- 线性反馈移位寄存器Verilog源程序,能够产生伪随机序列
伪随机序列
- 线形反馈移位寄存器(LFSR)是数字系统中一个重要的结构,本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and ci
实用verilog代码(乘法器,触发器,FIFO等)
- 本文件包含一些实用verilog程序代码,包括乘法器,除法器,伽罗瓦域乘法器,CORDIC数字计算机的设计,异步FIFO设计,伪随机序列应用设计,RS(204,188)译码器的设计,都是可综合的。对研究这部分的朋友有一定的帮助。
PN_Generator.rar
- 用Verilog编写的一个简单的产生伪随机序列的代码(m序列),比较实用。,Verilog prepared with the emergence of a simple pseudo-random code sequence (m sequence), more practical.
Verilog_code_for_AWGN.rar
- verilog实现awgn信道噪声的代码,支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
lfsr
- 此实验介绍了伪随机序列的产生原理,并用verilog语言将其编码实现,有详细的代码备注-This experiment introduces the principle of pseudo-random sequence and its encoded with the verilog language implementation, a detailed code Notes
lfsr
- 伪随机序列产生器-线性反馈移位寄存器,Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
LFSR
- verilog实现的8阶伪随机序列发生器,文件包含了三种主要模块:控制模块,ROM模块,线性反馈移位寄存器(LFSR)模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
c21_pn_code_generator
- 精通verilog HDL语言编程源码之7——伪随机序列应用设计-Proficient in programming language source verilog HDL of 7- the application of pseudo-random sequence design
fcsr
- 伪随机序列产生器-代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器-filtered 代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
prbsforip
- 本文设计了一种简捷而又高效的伪随机序列产生方法,最后通过统计对比,说名这种方法产生的随机序列不仅周期长 还具有两好的随机特性-This paper designed a simple and efficient method for the selection of pseudo-random sequence, and finally through statistical comparison, saying that this method of random sequence gen
Application_of_pseudo_random_sequence_verilog_desi
- 伪随机序列应用verilog设计.rar-Application of pseudo-random sequence verilog design.rar
prs8
- 伪随机序列verilog 以及 测试程序-Pseudo-random sequence verilog
prbs
- 伪随机二进制序列发生器的Verilog源码,带测试文件,并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
Verilog
- 本程序使用verilog语言实现了对伪随机序列的曼彻斯特编码-This program uses the verilog language to achieve the Manchester encoding of the pseudo-random sequence
pncode
- verilog hdl编写的伪随机序列产生程序;包含测试文件;-Verilog HDL;PN code
randomization
- 伪随机序列应用设计:利用verilog代码实现伪随机信号的产生-Pseudo-random sequence application design: the use of pseudo-random signals verilog code generation
m_sequence_fpga
- 采用Verilog语言编写的伪随机序列——m序列,可用作通信系统输入数据源。-Use Verilog language- m sequence pseudo random sequence, and can be used as input data sources in communication system.
20180125_5M_01
- 基于verilog产生伪随机二进制序列,序列速率为5M(A pseudo-random binary sequence based on verilog.)