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DDS
- 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
cordic
- 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
matlab-gmsk
- 基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.-Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the s
LPC213X_ARM_FFT_IFFT_VC6.0_proteus
- 内附使用说明，基于LPC213X ARM的FFT程序，ADS1.2工程，带proteus仿真，精确测量输入信号频率，带labvieFFT/IFFT仿真，VC6工程正余弦参数表生成程序，VC6工程的FFT/IFFT DLL库-with README inside,FFT program, ADS1.2 project LPC213X ARM-based, with proteus simulation, accurate measurement of the frequency of the in
cost
- 余弦信号发生器 在QUARTUS上生成余弦波 用于产生跟正弦正交的信号-Cosine signal generator cosine wave is used to produce with sinusoidal quadrature signal generated in the Quartus on
table-for-sin-functionof-
- DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率-Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own
sin_rom
- 在rom文件中生成正弦波COE文件，在Matlab中生成正余弦波形的浮点值，并量化为16bit定点波形数值- Generate sine wave COE file in rom file
sincos-generator
- 用C语言编写的用于生成通讯信号电源正余弦波形的程序-Programed using C to generate sin/cos wave data for communication power supply
cordic
- 生成正余弦函数，根据cordic算法可以生成sin和cos(Generating sin or cos function)
sincos
- 实现正余弦函数Verilog语言的生成...............(sine wave generator by using verilog)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da